diff options
Diffstat (limited to 'src/gallium/drivers/radeonsi/evergreen_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/evergreen_state.c | 358 |
1 files changed, 0 insertions, 358 deletions
diff --git a/src/gallium/drivers/radeonsi/evergreen_state.c b/src/gallium/drivers/radeonsi/evergreen_state.c index 2b3403be3a7..b85e8bda041 100644 --- a/src/gallium/drivers/radeonsi/evergreen_state.c +++ b/src/gallium/drivers/radeonsi/evergreen_state.c @@ -1254,363 +1254,6 @@ static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample { } -static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, - const struct pipe_framebuffer_state *state, int cb) -{ - struct r600_resource_texture *rtex; - struct r600_surface *surf; - unsigned level = state->cbufs[cb]->u.tex.level; - unsigned pitch, slice; - unsigned color_info, color_attrib; - unsigned format, swap, ntype, endian; - uint64_t offset; - unsigned blocksize; - const struct util_format_description *desc; - int i; - unsigned blend_clamp = 0, blend_bypass = 0; - - surf = (struct r600_surface *)state->cbufs[cb]; - rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; - blocksize = util_format_get_blocksize(rtex->real_format); - - if (rtex->depth) - rctx->have_depth_fb = TRUE; - - if (rtex->depth && !rtex->is_flushing_texture) { - r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE); - rtex = rtex->flushed_depth_texture; - } - - offset = rtex->surface.level[level].offset; - if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { - offset += rtex->surface.level[level].slice_size * - state->cbufs[cb]->u.tex.first_layer; - } - pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; - slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; - if (slice) { - slice = slice - 1; - } - - color_attrib = S_028C74_TILE_MODE_INDEX(8); - switch (rtex->surface.level[level].mode) { - case RADEON_SURF_MODE_LINEAR_ALIGNED: - color_attrib = S_028C74_TILE_MODE_INDEX(8); - break; - case RADEON_SURF_MODE_1D: - color_attrib = S_028C74_TILE_MODE_INDEX(9); - break; - case RADEON_SURF_MODE_2D: - if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) { - switch (blocksize) { - case 1: - color_attrib = S_028C74_TILE_MODE_INDEX(10); - break; - case 2: - color_attrib = S_028C74_TILE_MODE_INDEX(11); - break; - case 4: - color_attrib = S_028C74_TILE_MODE_INDEX(12); - break; - } - break; - } else switch (blocksize) { - case 1: - color_attrib = S_028C74_TILE_MODE_INDEX(14); - break; - case 2: - color_attrib = S_028C74_TILE_MODE_INDEX(15); - break; - case 4: - color_attrib = S_028C74_TILE_MODE_INDEX(16); - break; - case 8: - color_attrib = S_028C74_TILE_MODE_INDEX(17); - break; - default: - color_attrib = S_028C74_TILE_MODE_INDEX(13); - } - break; - } - - desc = util_format_description(surf->base.format); - for (i = 0; i < 4; i++) { - if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { - break; - } - } - if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { - ntype = V_028C70_NUMBER_FLOAT; - } else { - ntype = V_028C70_NUMBER_UNORM; - if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) - ntype = V_028C70_NUMBER_SRGB; - else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { - if (desc->channel[i].normalized) - ntype = V_028C70_NUMBER_SNORM; - else if (desc->channel[i].pure_integer) - ntype = V_028C70_NUMBER_SINT; - } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { - if (desc->channel[i].normalized) - ntype = V_028C70_NUMBER_UNORM; - else if (desc->channel[i].pure_integer) - ntype = V_028C70_NUMBER_UINT; - } - } - - format = si_translate_colorformat(surf->base.format); - swap = si_translate_colorswap(surf->base.format); - if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { - endian = V_028C70_ENDIAN_NONE; - } else { - endian = si_colorformat_endian_swap(format); - } - - /* blend clamp should be set for all NORM/SRGB types */ - if (ntype == V_028C70_NUMBER_UNORM || - ntype == V_028C70_NUMBER_SNORM || - ntype == V_028C70_NUMBER_SRGB) - blend_clamp = 1; - - /* set blend bypass according to docs if SINT/UINT or - 8/24 COLOR variants */ - if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || - format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || - format == V_028C70_COLOR_X24_8_32_FLOAT) { - blend_clamp = 0; - blend_bypass = 1; - } - - color_info = S_028C70_FORMAT(format) | - S_028C70_COMP_SWAP(swap) | - S_028C70_BLEND_CLAMP(blend_clamp) | - S_028C70_BLEND_BYPASS(blend_bypass) | - S_028C70_NUMBER_TYPE(ntype) | - S_028C70_ENDIAN(endian); - - rctx->alpha_ref_dirty = true; - - offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); - offset >>= 8; - - /* FIXME handle enabling of CB beyond BASE8 which has different offset */ - r600_pipe_state_add_reg(rstate, - R_028C60_CB_COLOR0_BASE + cb * 0x3C, - offset, &rtex->resource, RADEON_USAGE_READWRITE); - r600_pipe_state_add_reg(rstate, - R_028C64_CB_COLOR0_PITCH + cb * 0x3C, - S_028C64_TILE_MAX(pitch), - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028C68_CB_COLOR0_SLICE + cb * 0x3C, - S_028C68_TILE_MAX(slice), - NULL, 0); - if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { - r600_pipe_state_add_reg(rstate, - R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, - 0x00000000, NULL, 0); - } else { - r600_pipe_state_add_reg(rstate, - R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, - S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | - S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer), - NULL, 0); - } - r600_pipe_state_add_reg(rstate, - R_028C70_CB_COLOR0_INFO + cb * 0x3C, - color_info, &rtex->resource, RADEON_USAGE_READWRITE); - r600_pipe_state_add_reg(rstate, - R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, - color_attrib, - &rtex->resource, RADEON_USAGE_READWRITE); -} - -static void si_db(struct r600_context *rctx, struct r600_pipe_state *rstate, - const struct pipe_framebuffer_state *state) -{ - struct r600_resource_texture *rtex; - struct r600_surface *surf; - unsigned level, first_layer, pitch, slice, format; - uint32_t db_z_info, stencil_info; - uint64_t offset; - - if (state->zsbuf == NULL) { - r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0); - r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, 0, NULL, 0); - return; - } - - surf = (struct r600_surface *)state->zsbuf; - level = surf->base.u.tex.level; - rtex = (struct r600_resource_texture*)surf->base.texture; - - first_layer = surf->base.u.tex.first_layer; - format = si_translate_dbformat(rtex->real_format); - - offset = r600_resource_va(rctx->context.screen, surf->base.texture); - offset += rtex->surface.level[level].offset; - pitch = (rtex->surface.level[level].nblk_x / 8) - 1; - slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; - if (slice) { - slice = slice - 1; - } - offset >>= 8; - - r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE, - offset, &rtex->resource, RADEON_USAGE_READWRITE); - r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE, - offset, &rtex->resource, RADEON_USAGE_READWRITE); - r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, - S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) | - S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer), - NULL, 0); - - db_z_info = S_028040_FORMAT(format); - stencil_info = S_028044_FORMAT(rtex->stencil != 0); - - switch (format) { - case V_028040_Z_16: - db_z_info |= S_028040_TILE_MODE_INDEX(5); - stencil_info |= S_028044_TILE_MODE_INDEX(5); - break; - case V_028040_Z_24: - case V_028040_Z_32_FLOAT: - db_z_info |= S_028040_TILE_MODE_INDEX(6); - stencil_info |= S_028044_TILE_MODE_INDEX(6); - break; - default: - db_z_info |= S_028040_TILE_MODE_INDEX(7); - stencil_info |= S_028044_TILE_MODE_INDEX(7); - } - - if (rtex->stencil) { - uint64_t stencil_offset = - r600_texture_get_offset(rtex->stencil, level, first_layer); - - stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil); - stencil_offset >>= 8; - - r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE, - stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE); - r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE, - stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE); - r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, - stencil_info, NULL, 0); - } else { - r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, - 0, NULL, 0); - } - - if (format != ~0U) { - r600_pipe_state_add_reg(rstate, R_02803C_DB_DEPTH_INFO, 0x1, NULL, 0); - r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, db_z_info, NULL, 0); - r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, - S_028058_PITCH_TILE_MAX(pitch), - NULL, 0); - r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, - S_02805C_SLICE_TILE_MAX(slice), - NULL, 0); - - } else { - r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0); - } -} - -static void evergreen_set_framebuffer_state(struct pipe_context *ctx, - const struct pipe_framebuffer_state *state) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); - uint32_t shader_mask, tl, br; - int tl_x, tl_y, br_x, br_y; - - if (rstate == NULL) - return; - - r600_flush_framebuffer(rctx, false); - - /* unreference old buffer and reference new one */ - rstate->id = R600_PIPE_STATE_FRAMEBUFFER; - - util_copy_framebuffer_state(&rctx->framebuffer, state); - - /* build states */ - rctx->have_depth_fb = 0; - rctx->nr_cbufs = state->nr_cbufs; - for (int i = 0; i < state->nr_cbufs; i++) { - evergreen_cb(rctx, rstate, state, i); - } - si_db(rctx, rstate, state); - - shader_mask = 0; - for (int i = 0; i < state->nr_cbufs; i++) { - shader_mask |= 0xf << (i * 4); - } - tl_x = 0; - tl_y = 0; - br_x = state->width; - br_y = state->height; -#if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */ - /* EG hw workaround */ - if (br_x == 0) - tl_x = 1; - if (br_y == 0) - tl_y = 1; - /* cayman hw workaround */ - if (rctx->chip_class == CAYMAN) { - if (br_x == 1 && br_y == 1) - br_x = 2; - } -#endif - tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y); - br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y); - - r600_pipe_state_add_reg(rstate, - R_028240_PA_SC_GENERIC_SCISSOR_TL, tl, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028244_PA_SC_GENERIC_SCISSOR_BR, br, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028030_PA_SC_SCREEN_SCISSOR_TL, tl, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028034_PA_SC_SCREEN_SCISSOR_BR, br, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028208_PA_SC_WINDOW_SCISSOR_BR, br, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028200_PA_SC_WINDOW_OFFSET, 0x00000000, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028230_PA_SC_EDGERULE, 0xAAAAAAAA, - NULL, 0); - - r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK, - shader_mask, NULL, 0); - - r600_pipe_state_add_reg(rstate, R_028BE0_PA_SC_AA_CONFIG, - 0x00000000, NULL, 0); - - free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); - rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; - r600_context_pipe_state_set(rctx, rstate); - - if (state->zsbuf) { - cayman_polygon_offset_update(rctx); - } -} - void cayman_init_state_functions(struct r600_context *rctx) { si_init_state_functions(rctx); @@ -1636,7 +1279,6 @@ void cayman_init_state_functions(struct r600_context *rctx) rctx->context.delete_vs_state = r600_delete_vs_shader; rctx->context.set_constant_buffer = r600_set_constant_buffer; rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view; - rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state; rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple; rctx->context.set_sample_mask = evergreen_set_sample_mask; rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref; |