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-rw-r--r--src/gallium/drivers/radeon/r600_pipe_common.h1
-rw-r--r--src/gallium/drivers/radeon/r600_texture.c4
2 files changed, 4 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index b391cbb82a6..fb52dfb5297 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -202,6 +202,7 @@ struct r600_fmask_info {
unsigned bank_height;
unsigned slice_tile_max;
unsigned tile_mode_index;
+ unsigned tile_swizzle;
};
struct r600_cmask_info {
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 07df2d43017..e3d462ea80a 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -757,6 +757,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
out->tile_mode_index = fmask.u.legacy.tiling_index[0];
out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
out->bank_height = fmask.u.legacy.bankh;
+ out->tile_swizzle = fmask.tile_swizzle;
out->alignment = MAX2(256, fmask.surf_alignment);
out->size = fmask.surf_size;
}
@@ -1447,7 +1448,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
struct pb_buffer *buf = NULL;
unsigned stride = 0, offset = 0;
unsigned array_mode;
- struct radeon_surf surface;
+ struct radeon_surf surface = {};
int r;
struct radeon_bo_metadata metadata = {};
struct r600_texture *rtex;
@@ -1511,6 +1512,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
assert(metadata.u.gfx9.swizzle_mode == surface.u.gfx9.surf.swizzle_mode);
}
+ assert(rtex->surface.tile_swizzle == 0);
return &rtex->resource.b.b;
}