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-rw-r--r--src/gallium/drivers/radeon/r600_texture.c10
-rw-r--r--src/gallium/drivers/radeon/radeon_winsys.h4
2 files changed, 4 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index c9c87c7dbb0..74977ea60fb 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -816,8 +816,8 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
/* HW bug on R6xx. */
if (rscreen->chip_class == R600 &&
- (rtex->surface.level[0].npix_x > 7680 ||
- rtex->surface.level[0].npix_y > 7680))
+ (rtex->resource.b.b.width0 > 7680 ||
+ rtex->resource.b.b.height0 > 7680))
return 0;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
@@ -973,7 +973,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
- "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+ "pitch_bytes=%u, mode=%u\n",
i, rtex->surface.level[i].offset,
rtex->surface.level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
@@ -981,7 +981,6 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.level[i].nblk_x,
rtex->surface.level[i].nblk_y,
- rtex->surface.level[i].nblk_z,
rtex->surface.level[i].pitch_bytes,
rtex->surface.level[i].mode);
@@ -992,7 +991,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
"slice_size=%"PRIu64", npix_x=%u, "
"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
- "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+ "pitch_bytes=%u, mode=%u\n",
i, rtex->surface.stencil_level[i].offset,
rtex->surface.stencil_level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
@@ -1000,7 +999,6 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.stencil_level[i].nblk_x,
rtex->surface.stencil_level[i].nblk_y,
- rtex->surface.stencil_level[i].nblk_z,
rtex->surface.stencil_level[i].pitch_bytes,
rtex->surface.stencil_level[i].mode);
}
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 4573efe14ed..a28bac1d8bc 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -280,12 +280,8 @@ struct radeon_surf_level {
uint64_t slice_size;
uint64_t dcc_offset;
uint64_t dcc_fast_clear_size;
- uint16_t npix_x;
- uint16_t npix_y;
- uint16_t npix_z;
uint16_t nblk_x;
uint16_t nblk_y;
- uint16_t nblk_z;
uint32_t pitch_bytes;
enum radeon_surf_mode mode;
bool dcc_enabled;