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-rw-r--r--src/gallium/drivers/radeon/r600_pipe_common.h2
-rw-r--r--src/gallium/drivers/radeon/r600_texture.c12
-rw-r--r--src/gallium/drivers/radeon/radeon_uvd.c6
-rw-r--r--src/gallium/drivers/radeon/radeon_uvd.h4
-rw-r--r--src/gallium/drivers/radeon/radeon_vce.c2
-rw-r--r--src/gallium/drivers/radeon/radeon_vce.h6
-rw-r--r--src/gallium/drivers/radeon/radeon_video.c2
-rw-r--r--src/gallium/drivers/radeon/radeon_video.h2
-rw-r--r--src/gallium/drivers/radeon/radeon_winsys.h79
9 files changed, 94 insertions, 21 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index f1c95037e7f..8d885ab9836 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -199,7 +199,7 @@ struct r600_texture {
unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
struct r600_texture *flushed_depth_texture;
boolean is_flushing_texture;
- struct radeon_surface surface;
+ struct radeon_surf surface;
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info fmask;
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index ab8ce7bd713..dc510c99749 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -119,7 +119,7 @@ static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned leve
}
static int r600_init_surface(struct r600_common_screen *rscreen,
- struct radeon_surface *surface,
+ struct radeon_surf *surface,
const struct pipe_resource *ptex,
unsigned array_mode,
bool is_flushed_depth)
@@ -234,7 +234,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
{
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = &rtex->resource;
- struct radeon_surface *surface = &rtex->surface;
+ struct radeon_surf *surface = &rtex->surface;
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
rscreen->ws->buffer_set_tiling(resource->buf,
@@ -280,7 +280,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
struct r600_fmask_info *out)
{
/* FMASK is allocated like an ordinary texture. */
- struct radeon_surface fmask = rtex->surface;
+ struct radeon_surf fmask = rtex->surface;
memset(out, 0, sizeof(*out));
@@ -570,7 +570,7 @@ r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned pitch_in_bytes_override,
struct pb_buffer *buf,
- struct radeon_surface *surface)
+ struct radeon_surf *surface)
{
struct r600_texture *rtex;
struct r600_resource *resource;
@@ -764,7 +764,7 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
- struct radeon_surface surface = {0};
+ struct radeon_surf surface = {0};
int r;
r = r600_init_surface(rscreen, &surface, templ,
@@ -790,7 +790,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
unsigned stride = 0;
unsigned array_mode;
enum radeon_bo_layout micro, macro;
- struct radeon_surface surface;
+ struct radeon_surf surface;
bool scanout;
int r;
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
index 4d4b54b3a56..be58d0b9ce3 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -870,7 +870,7 @@ error:
}
/* calculate top/bottom offset */
-static unsigned texture_offset(struct radeon_surface *surface, unsigned layer)
+static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
{
return surface->level[0].offset +
layer * surface->level[0].slice_size;
@@ -905,8 +905,8 @@ static unsigned bank_wh(unsigned bankwh)
/**
* fill decoding target field from the luma and chroma surfaces
*/
-void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma,
- struct radeon_surface *chroma)
+void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
+ struct radeon_surf *chroma)
{
msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
switch (luma->level[0].mode) {
diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h
index 41a6fb4a850..7442865c9ec 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.h
+++ b/src/gallium/drivers/radeon/radeon_uvd.h
@@ -353,6 +353,6 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
ruvd_set_dtb set_dtb);
/* fill decoding target field from the luma and chroma surfaces */
-void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma,
- struct radeon_surface *chroma);
+void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
+ struct radeon_surf *chroma);
#endif
diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
index 5f710e636c9..e220f40165b 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -337,7 +337,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
struct rvce_encoder *enc;
struct pipe_video_buffer *tmp_buf, templat = {};
- struct radeon_surface *tmp_surf;
+ struct radeon_surf *tmp_surf;
unsigned cpb_size;
if (!rscreen->info.vce_fw_version) {
diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h
index 7f0cd1fcc75..5c6317a972f 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -50,7 +50,7 @@ struct r600_common_screen;
/* driver dependent callback */
typedef void (*rvce_get_buffer)(struct pipe_resource *resource,
struct radeon_winsys_cs_handle **handle,
- struct radeon_surface **surface);
+ struct radeon_surf **surface);
/* Coded picture buffer slot */
struct rvce_cpb_slot {
@@ -88,8 +88,8 @@ struct rvce_encoder {
rvce_get_buffer get_buffer;
struct radeon_winsys_cs_handle* handle;
- struct radeon_surface* luma;
- struct radeon_surface* chroma;
+ struct radeon_surf* luma;
+ struct radeon_surf* chroma;
struct radeon_winsys_cs_handle* bs_handle;
unsigned bs_size;
diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
index 6ec10c1de6c..826e0763c08 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -132,7 +132,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
*/
void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
struct pb_buffer** buffers[VL_NUM_COMPONENTS],
- struct radeon_surface *surfaces[VL_NUM_COMPONENTS])
+ struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
{
unsigned best_tiling, best_wh, off;
unsigned size, alignment;
diff --git a/src/gallium/drivers/radeon/radeon_video.h b/src/gallium/drivers/radeon/radeon_video.h
index 6d0ff2834fb..c9ee67f07e8 100644
--- a/src/gallium/drivers/radeon/radeon_video.h
+++ b/src/gallium/drivers/radeon/radeon_video.h
@@ -68,7 +68,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
sumup their sizes and replace the backend buffers with a single bo */
void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
struct pb_buffer** buffers[VL_NUM_COMPONENTS],
- struct radeon_surface *surfaces[VL_NUM_COMPONENTS]);
+ struct radeon_surf *surfaces[VL_NUM_COMPONENTS]);
/* returns supported codecs and other parameters */
int rvid_get_video_param(struct pipe_screen *screen,
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index ee0a9040709..3bfbb6d75b7 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -41,7 +41,6 @@
*/
#include "pipebuffer/pb_buffer.h"
-#include "radeon_surface.h"
#define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
@@ -246,6 +245,80 @@ enum radeon_feature_id {
RADEON_FID_R300_CMASK_ACCESS,
};
+#define RADEON_SURF_MAX_LEVEL 32
+
+#define RADEON_SURF_TYPE_MASK 0xFF
+#define RADEON_SURF_TYPE_SHIFT 0
+#define RADEON_SURF_TYPE_1D 0
+#define RADEON_SURF_TYPE_2D 1
+#define RADEON_SURF_TYPE_3D 2
+#define RADEON_SURF_TYPE_CUBEMAP 3
+#define RADEON_SURF_TYPE_1D_ARRAY 4
+#define RADEON_SURF_TYPE_2D_ARRAY 5
+#define RADEON_SURF_MODE_MASK 0xFF
+#define RADEON_SURF_MODE_SHIFT 8
+#define RADEON_SURF_MODE_LINEAR 0
+#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
+#define RADEON_SURF_MODE_1D 2
+#define RADEON_SURF_MODE_2D 3
+#define RADEON_SURF_SCANOUT (1 << 16)
+#define RADEON_SURF_ZBUFFER (1 << 17)
+#define RADEON_SURF_SBUFFER (1 << 18)
+#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
+#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
+#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
+#define RADEON_SURF_FMASK (1 << 21)
+
+#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
+#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
+#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
+
+struct radeon_surf_level {
+ uint64_t offset;
+ uint64_t slice_size;
+ uint32_t npix_x;
+ uint32_t npix_y;
+ uint32_t npix_z;
+ uint32_t nblk_x;
+ uint32_t nblk_y;
+ uint32_t nblk_z;
+ uint32_t pitch_bytes;
+ uint32_t mode;
+};
+
+struct radeon_surf {
+ /* These are inputs to the calculator. */
+ uint32_t npix_x;
+ uint32_t npix_y;
+ uint32_t npix_z;
+ uint32_t blk_w;
+ uint32_t blk_h;
+ uint32_t blk_d;
+ uint32_t array_size;
+ uint32_t last_level;
+ uint32_t bpe;
+ uint32_t nsamples;
+ uint32_t flags;
+
+ /* These are return values. Some of them can be set by the caller, but
+ * they will be treated as hints (e.g. bankw, bankh) and might be
+ * changed by the calculator.
+ */
+ uint64_t bo_size;
+ uint64_t bo_alignment;
+ /* This applies to EG and later. */
+ uint32_t bankw;
+ uint32_t bankh;
+ uint32_t mtilea;
+ uint32_t tile_split;
+ uint32_t stencil_tile_split;
+ uint64_t stencil_offset;
+ struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
+ struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
+ uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
+ uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
+};
+
struct radeon_winsys {
/**
* The screen object this winsys was created for
@@ -576,7 +649,7 @@ struct radeon_winsys {
* \param surf Surface structure ptr
*/
int (*surface_init)(struct radeon_winsys *ws,
- struct radeon_surface *surf);
+ struct radeon_surf *surf);
/**
* Find best values for a surface
@@ -585,7 +658,7 @@ struct radeon_winsys {
* \param surf Surface structure ptr
*/
int (*surface_best)(struct radeon_winsys *ws,
- struct radeon_surface *surf);
+ struct radeon_surf *surf);
uint64_t (*query_value)(struct radeon_winsys *ws,
enum radeon_value_id value);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 13:53:25 +0000