1 files changed, 109 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp
new file mode 100644
index 00000000000..bcee89c4f91
--- /dev/null
+++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp
@@ -0,0 +1,109 @@
+//===-- R600InstrInfo.cpp - TODO: Add brief description -------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// TODO: Add full description
+//
+//===----------------------------------------------------------------------===//
+
+#include "R600InstrInfo.h"
+#include "AMDGPUTargetMachine.h"
+#include "R600RegisterInfo.h"
+
+using namespace llvm;
+
+R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
+  : AMDGPUInstrInfo(tm),
+    RI(tm, *this),
+    TM(tm)
+  { }
+
+const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const
+{
+  return RI;
+}
+
+bool R600InstrInfo::isTrig(const MachineInstr &MI) const
+{
+  return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
+}
+
+void
+R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MI, DebugLoc DL,
+                           unsigned DestReg, unsigned SrcReg,
+                           bool KillSrc) const
+{
+  if (!TargetRegisterInfo::isVirtualRegister(SrcReg)
+      && AMDIL::GPRI32RegClass.contains(SrcReg)) {
+    SrcReg = AMDIL::T0_X;
+  }
+  BuildMI(MBB, MI, DL, get(AMDIL::MOV), DestReg)
+    .addReg(SrcReg, getKillRegState(KillSrc));
+}
+
+unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
+{
+  switch (opcode) {
+    default: return AMDGPUInstrInfo::getISAOpcode(opcode);
+    case AMDIL::CUSTOM_ADD_i32:
+      return AMDIL::ADD_INT;
+    case AMDIL::CUSTOM_XOR_i32:
+      return AMDIL::XOR_INT;
+    case AMDIL::MOVE_f32:
+    case AMDIL::MOVE_i32:
+      return AMDIL::MOV;
+    case AMDIL::SHR_i32:
+      return getLSHRop();
+  }
+}
+
+unsigned R600InstrInfo::getLSHRop() const
+{
+  unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
+  if (gen < AMDILDeviceInfo::HD5XXX) {
+    return AMDIL::LSHR_r600;
+  } else {
+    return AMDIL::LSHR_eg;
+  }
+}
+
+unsigned R600InstrInfo::getMULHI_UINT() const
+{
+  unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
+
+  if (gen < AMDILDeviceInfo::HD5XXX) {
+    return AMDIL::MULHI_UINT_r600;
+  } else {
+    return AMDIL::MULHI_UINT_eg;
+  }
+}
+
+unsigned R600InstrInfo::getMULLO_UINT() const
+{
+  unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
+
+  if (gen < AMDILDeviceInfo::HD5XXX) {
+    return AMDIL::MULLO_UINT_r600;
+  } else {
+    return AMDIL::MULLO_UINT_eg;
+  }
+}
+
+unsigned R600InstrInfo::getRECIP_UINT() const
+{
+  const AMDILDevice * dev = TM.getSubtarget<AMDILSubtarget>().device();
+
+  if (dev->getGeneration() < AMDILDeviceInfo::HD5XXX) {
+    return AMDIL::RECIP_UINT_r600;
+  } else if (dev->getDeviceFlag() != OCL_DEVICE_CAYMAN) {
+    return AMDIL::RECIP_UINT_eg;
+  } else {
+    return AMDIL::RECIP_UINT_cm;
+  }
+}