diff options
Diffstat (limited to 'src/gallium/drivers/radeon/AMDILISelLowering.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILISelLowering.cpp | 510 |
1 files changed, 2 insertions, 508 deletions
diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index 3cc79452d43..12b3dce5ee8 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -670,45 +670,13 @@ AMDILTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { default: return 0; - case AMDILISD::INTTOANY: return "AMDILISD::INTTOANY"; - case AMDILISD::DP_TO_FP: return "AMDILISD::DP_TO_FP"; - case AMDILISD::FP_TO_DP: return "AMDILISD::FP_TO_DP"; - case AMDILISD::BITCONV: return "AMDILISD::BITCONV"; - case AMDILISD::CMOV: return "AMDILISD::CMOV"; case AMDILISD::CMOVLOG: return "AMDILISD::CMOVLOG"; - case AMDILISD::INEGATE: return "AMDILISD::INEGATE"; case AMDILISD::MAD: return "AMDILISD::MAD"; - case AMDILISD::UMAD: return "AMDILISD::UMAD"; case AMDILISD::CALL: return "AMDILISD::CALL"; - case AMDILISD::RET: return "AMDILISD::RET"; - case AMDILISD::IFFB_HI: return "AMDILISD::IFFB_HI"; - case AMDILISD::IFFB_LO: return "AMDILISD::IFFB_LO"; - case AMDILISD::ADD: return "AMDILISD::ADD"; + case AMDILISD::SELECT_CC: return "AMDILISD::SELECT_CC"; case AMDILISD::UMUL: return "AMDILISD::UMUL"; - case AMDILISD::AND: return "AMDILISD::AND"; - case AMDILISD::OR: return "AMDILISD::OR"; - case AMDILISD::NOT: return "AMDILISD::NOT"; - case AMDILISD::XOR: return "AMDILISD::XOR"; case AMDILISD::DIV_INF: return "AMDILISD::DIV_INF"; - case AMDILISD::SMAX: return "AMDILISD::SMAX"; - case AMDILISD::PHIMOVE: return "AMDILISD::PHIMOVE"; - case AMDILISD::MOVE: return "AMDILISD::MOVE"; case AMDILISD::VBUILD: return "AMDILISD::VBUILD"; - case AMDILISD::VEXTRACT: return "AMDILISD::VEXTRACT"; - case AMDILISD::VINSERT: return "AMDILISD::VINSERT"; - case AMDILISD::VCONCAT: return "AMDILISD::VCONCAT"; - case AMDILISD::LCREATE: return "AMDILISD::LCREATE"; - case AMDILISD::LCOMPHI: return "AMDILISD::LCOMPHI"; - case AMDILISD::LCOMPLO: return "AMDILISD::LCOMPLO"; - case AMDILISD::DCREATE: return "AMDILISD::DCREATE"; - case AMDILISD::DCOMPHI: return "AMDILISD::DCOMPHI"; - case AMDILISD::DCOMPLO: return "AMDILISD::DCOMPLO"; - case AMDILISD::LCREATE2: return "AMDILISD::LCREATE2"; - case AMDILISD::LCOMPHI2: return "AMDILISD::LCOMPHI2"; - case AMDILISD::LCOMPLO2: return "AMDILISD::LCOMPLO2"; - case AMDILISD::DCREATE2: return "AMDILISD::DCREATE2"; - case AMDILISD::DCOMPHI2: return "AMDILISD::DCOMPHI2"; - case AMDILISD::DCOMPLO2: return "AMDILISD::DCOMPLO2"; case AMDILISD::CMP: return "AMDILISD::CMP"; case AMDILISD::IL_CC_I_LT: return "AMDILISD::IL_CC_I_LT"; case AMDILISD::IL_CC_I_LE: return "AMDILISD::IL_CC_I_LE"; @@ -718,107 +686,6 @@ AMDILTargetLowering::getTargetNodeName(unsigned Opcode) const case AMDILISD::IL_CC_I_NE: return "AMDILISD::IL_CC_I_NE"; case AMDILISD::RET_FLAG: return "AMDILISD::RET_FLAG"; case AMDILISD::BRANCH_COND: return "AMDILISD::BRANCH_COND"; - case AMDILISD::LOOP_NZERO: return "AMDILISD::LOOP_NZERO"; - case AMDILISD::LOOP_ZERO: return "AMDILISD::LOOP_ZERO"; - case AMDILISD::LOOP_CMP: return "AMDILISD::LOOP_CMP"; - case AMDILISD::ADDADDR: return "AMDILISD::ADDADDR"; - case AMDILISD::ATOM_G_ADD: return "AMDILISD::ATOM_G_ADD"; - case AMDILISD::ATOM_G_AND: return "AMDILISD::ATOM_G_AND"; - case AMDILISD::ATOM_G_CMPXCHG: return "AMDILISD::ATOM_G_CMPXCHG"; - case AMDILISD::ATOM_G_DEC: return "AMDILISD::ATOM_G_DEC"; - case AMDILISD::ATOM_G_INC: return "AMDILISD::ATOM_G_INC"; - case AMDILISD::ATOM_G_MAX: return "AMDILISD::ATOM_G_MAX"; - case AMDILISD::ATOM_G_UMAX: return "AMDILISD::ATOM_G_UMAX"; - case AMDILISD::ATOM_G_MIN: return "AMDILISD::ATOM_G_MIN"; - case AMDILISD::ATOM_G_UMIN: return "AMDILISD::ATOM_G_UMIN"; - case AMDILISD::ATOM_G_OR: return "AMDILISD::ATOM_G_OR"; - case AMDILISD::ATOM_G_SUB: return "AMDILISD::ATOM_G_SUB"; - case AMDILISD::ATOM_G_RSUB: return "AMDILISD::ATOM_G_RSUB"; - case AMDILISD::ATOM_G_XCHG: return "AMDILISD::ATOM_G_XCHG"; - case AMDILISD::ATOM_G_XOR: return "AMDILISD::ATOM_G_XOR"; - case AMDILISD::ATOM_G_ADD_NORET: return "AMDILISD::ATOM_G_ADD_NORET"; - case AMDILISD::ATOM_G_AND_NORET: return "AMDILISD::ATOM_G_AND_NORET"; - case AMDILISD::ATOM_G_CMPXCHG_NORET: return "AMDILISD::ATOM_G_CMPXCHG_NORET"; - case AMDILISD::ATOM_G_DEC_NORET: return "AMDILISD::ATOM_G_DEC_NORET"; - case AMDILISD::ATOM_G_INC_NORET: return "AMDILISD::ATOM_G_INC_NORET"; - case AMDILISD::ATOM_G_MAX_NORET: return "AMDILISD::ATOM_G_MAX_NORET"; - case AMDILISD::ATOM_G_UMAX_NORET: return "AMDILISD::ATOM_G_UMAX_NORET"; - case AMDILISD::ATOM_G_MIN_NORET: return "AMDILISD::ATOM_G_MIN_NORET"; - case AMDILISD::ATOM_G_UMIN_NORET: return "AMDILISD::ATOM_G_UMIN_NORET"; - case AMDILISD::ATOM_G_OR_NORET: return "AMDILISD::ATOM_G_OR_NORET"; - case AMDILISD::ATOM_G_SUB_NORET: return "AMDILISD::ATOM_G_SUB_NORET"; - case AMDILISD::ATOM_G_RSUB_NORET: return "AMDILISD::ATOM_G_RSUB_NORET"; - case AMDILISD::ATOM_G_XCHG_NORET: return "AMDILISD::ATOM_G_XCHG_NORET"; - case AMDILISD::ATOM_G_XOR_NORET: return "AMDILISD::ATOM_G_XOR_NORET"; - case AMDILISD::ATOM_L_ADD: return "AMDILISD::ATOM_L_ADD"; - case AMDILISD::ATOM_L_AND: return "AMDILISD::ATOM_L_AND"; - case AMDILISD::ATOM_L_CMPXCHG: return "AMDILISD::ATOM_L_CMPXCHG"; - case AMDILISD::ATOM_L_DEC: return "AMDILISD::ATOM_L_DEC"; - case AMDILISD::ATOM_L_INC: return "AMDILISD::ATOM_L_INC"; - case AMDILISD::ATOM_L_MAX: return "AMDILISD::ATOM_L_MAX"; - case AMDILISD::ATOM_L_UMAX: return "AMDILISD::ATOM_L_UMAX"; - case AMDILISD::ATOM_L_MIN: return "AMDILISD::ATOM_L_MIN"; - case AMDILISD::ATOM_L_UMIN: return "AMDILISD::ATOM_L_UMIN"; - case AMDILISD::ATOM_L_OR: return "AMDILISD::ATOM_L_OR"; - case AMDILISD::ATOM_L_SUB: return "AMDILISD::ATOM_L_SUB"; - case AMDILISD::ATOM_L_RSUB: return "AMDILISD::ATOM_L_RSUB"; - case AMDILISD::ATOM_L_XCHG: return "AMDILISD::ATOM_L_XCHG"; - case AMDILISD::ATOM_L_XOR: return "AMDILISD::ATOM_L_XOR"; - case AMDILISD::ATOM_L_ADD_NORET: return "AMDILISD::ATOM_L_ADD_NORET"; - case AMDILISD::ATOM_L_AND_NORET: return "AMDILISD::ATOM_L_AND_NORET"; - case AMDILISD::ATOM_L_CMPXCHG_NORET: return "AMDILISD::ATOM_L_CMPXCHG_NORET"; - case AMDILISD::ATOM_L_DEC_NORET: return "AMDILISD::ATOM_L_DEC_NORET"; - case AMDILISD::ATOM_L_INC_NORET: return "AMDILISD::ATOM_L_INC_NORET"; - case AMDILISD::ATOM_L_MAX_NORET: return "AMDILISD::ATOM_L_MAX_NORET"; - case AMDILISD::ATOM_L_UMAX_NORET: return "AMDILISD::ATOM_L_UMAX_NORET"; - case AMDILISD::ATOM_L_MIN_NORET: return "AMDILISD::ATOM_L_MIN_NORET"; - case AMDILISD::ATOM_L_UMIN_NORET: return "AMDILISD::ATOM_L_UMIN_NORET"; - case AMDILISD::ATOM_L_OR_NORET: return "AMDILISD::ATOM_L_OR_NORET"; - case AMDILISD::ATOM_L_SUB_NORET: return "AMDILISD::ATOM_L_SUB_NORET"; - case AMDILISD::ATOM_L_RSUB_NORET: return "AMDILISD::ATOM_L_RSUB_NORET"; - case AMDILISD::ATOM_L_XCHG_NORET: return "AMDILISD::ATOM_L_XCHG_NORET"; - case AMDILISD::ATOM_R_ADD: return "AMDILISD::ATOM_R_ADD"; - case AMDILISD::ATOM_R_AND: return "AMDILISD::ATOM_R_AND"; - case AMDILISD::ATOM_R_CMPXCHG: return "AMDILISD::ATOM_R_CMPXCHG"; - case AMDILISD::ATOM_R_DEC: return "AMDILISD::ATOM_R_DEC"; - case AMDILISD::ATOM_R_INC: return "AMDILISD::ATOM_R_INC"; - case AMDILISD::ATOM_R_MAX: return "AMDILISD::ATOM_R_MAX"; - case AMDILISD::ATOM_R_UMAX: return "AMDILISD::ATOM_R_UMAX"; - case AMDILISD::ATOM_R_MIN: return "AMDILISD::ATOM_R_MIN"; - case AMDILISD::ATOM_R_UMIN: return "AMDILISD::ATOM_R_UMIN"; - case AMDILISD::ATOM_R_OR: return "AMDILISD::ATOM_R_OR"; - case AMDILISD::ATOM_R_MSKOR: return "AMDILISD::ATOM_R_MSKOR"; - case AMDILISD::ATOM_R_SUB: return "AMDILISD::ATOM_R_SUB"; - case AMDILISD::ATOM_R_RSUB: return "AMDILISD::ATOM_R_RSUB"; - case AMDILISD::ATOM_R_XCHG: return "AMDILISD::ATOM_R_XCHG"; - case AMDILISD::ATOM_R_XOR: return "AMDILISD::ATOM_R_XOR"; - case AMDILISD::ATOM_R_ADD_NORET: return "AMDILISD::ATOM_R_ADD_NORET"; - case AMDILISD::ATOM_R_AND_NORET: return "AMDILISD::ATOM_R_AND_NORET"; - case AMDILISD::ATOM_R_CMPXCHG_NORET: return "AMDILISD::ATOM_R_CMPXCHG_NORET"; - case AMDILISD::ATOM_R_DEC_NORET: return "AMDILISD::ATOM_R_DEC_NORET"; - case AMDILISD::ATOM_R_INC_NORET: return "AMDILISD::ATOM_R_INC_NORET"; - case AMDILISD::ATOM_R_MAX_NORET: return "AMDILISD::ATOM_R_MAX_NORET"; - case AMDILISD::ATOM_R_UMAX_NORET: return "AMDILISD::ATOM_R_UMAX_NORET"; - case AMDILISD::ATOM_R_MIN_NORET: return "AMDILISD::ATOM_R_MIN_NORET"; - case AMDILISD::ATOM_R_UMIN_NORET: return "AMDILISD::ATOM_R_UMIN_NORET"; - case AMDILISD::ATOM_R_OR_NORET: return "AMDILISD::ATOM_R_OR_NORET"; - case AMDILISD::ATOM_R_MSKOR_NORET: return "AMDILISD::ATOM_R_MSKOR_NORET"; - case AMDILISD::ATOM_R_SUB_NORET: return "AMDILISD::ATOM_R_SUB_NORET"; - case AMDILISD::ATOM_R_RSUB_NORET: return "AMDILISD::ATOM_R_RSUB_NORET"; - case AMDILISD::ATOM_R_XCHG_NORET: return "AMDILISD::ATOM_R_XCHG_NORET"; - case AMDILISD::ATOM_R_XOR_NORET: return "AMDILISD::ATOM_R_XOR_NORET"; - case AMDILISD::APPEND_ALLOC: return "AMDILISD::APPEND_ALLOC"; - case AMDILISD::APPEND_ALLOC_NORET: return "AMDILISD::APPEND_ALLOC_NORET"; - case AMDILISD::APPEND_CONSUME: return "AMDILISD::APPEND_CONSUME"; - case AMDILISD::APPEND_CONSUME_NORET: return "AMDILISD::APPEND_CONSUME_NORET"; - case AMDILISD::IMAGE2D_READ: return "AMDILISD::IMAGE2D_READ"; - case AMDILISD::IMAGE2D_WRITE: return "AMDILISD::IMAGE2D_WRITE"; - case AMDILISD::IMAGE2D_INFO0: return "AMDILISD::IMAGE2D_INFO0"; - case AMDILISD::IMAGE2D_INFO1: return "AMDILISD::IMAGE2D_INFO1"; - case AMDILISD::IMAGE3D_READ: return "AMDILISD::IMAGE3D_READ"; - case AMDILISD::IMAGE3D_WRITE: return "AMDILISD::IMAGE3D_WRITE"; - case AMDILISD::IMAGE3D_INFO0: return "AMDILISD::IMAGE3D_INFO0"; - case AMDILISD::IMAGE3D_INFO1: return "AMDILISD::IMAGE3D_INFO1"; }; } @@ -826,380 +693,7 @@ bool AMDILTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const { - if (Intrinsic <= AMDGPUIntrinsic::last_non_AMDIL_intrinsic - || Intrinsic > AMDGPUIntrinsic::num_AMDIL_intrinsics) { - return false; - } - bool bitCastToInt = false; - unsigned IntNo; - bool isRet = true; - const AMDILSubtarget *STM = &this->getTargetMachine() - .getSubtarget<AMDILSubtarget>(); - switch (Intrinsic) { - default: return false; // Don't custom lower most intrinsics. - case AMDGPUIntrinsic::AMDIL_atomic_add_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_add_gu32: - IntNo = AMDILISD::ATOM_G_ADD; break; - case AMDGPUIntrinsic::AMDIL_atomic_add_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_add_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_ADD_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_add_lu32: - case AMDGPUIntrinsic::AMDIL_atomic_add_li32: - IntNo = AMDILISD::ATOM_L_ADD; break; - case AMDGPUIntrinsic::AMDIL_atomic_add_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_add_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_ADD_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_add_ru32: - case AMDGPUIntrinsic::AMDIL_atomic_add_ri32: - IntNo = AMDILISD::ATOM_R_ADD; break; - case AMDGPUIntrinsic::AMDIL_atomic_add_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_add_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_ADD_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_and_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_and_gu32: - IntNo = AMDILISD::ATOM_G_AND; break; - case AMDGPUIntrinsic::AMDIL_atomic_and_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_and_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_AND_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_and_li32: - case AMDGPUIntrinsic::AMDIL_atomic_and_lu32: - IntNo = AMDILISD::ATOM_L_AND; break; - case AMDGPUIntrinsic::AMDIL_atomic_and_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_and_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_AND_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_and_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_and_ru32: - IntNo = AMDILISD::ATOM_R_AND; break; - case AMDGPUIntrinsic::AMDIL_atomic_and_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_and_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_AND_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_gu32: - IntNo = AMDILISD::ATOM_G_CMPXCHG; break; - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_CMPXCHG_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_li32: - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_lu32: - IntNo = AMDILISD::ATOM_L_CMPXCHG; break; - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_CMPXCHG_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_ru32: - IntNo = AMDILISD::ATOM_R_CMPXCHG; break; - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_CMPXCHG_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_dec_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_dec_gu32: - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_G_DEC; - } else { - IntNo = AMDILISD::ATOM_G_SUB; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_dec_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_dec_gu32_noret: - isRet = false; - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_G_DEC_NORET; - } else { - IntNo = AMDILISD::ATOM_G_SUB_NORET; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_dec_li32: - case AMDGPUIntrinsic::AMDIL_atomic_dec_lu32: - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_L_DEC; - } else { - IntNo = AMDILISD::ATOM_L_SUB; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_dec_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_dec_lu32_noret: - isRet = false; - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_L_DEC_NORET; - } else { - IntNo = AMDILISD::ATOM_L_SUB_NORET; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_dec_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_dec_ru32: - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_R_DEC; - } else { - IntNo = AMDILISD::ATOM_R_SUB; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_dec_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_dec_ru32_noret: - isRet = false; - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_R_DEC_NORET; - } else { - IntNo = AMDILISD::ATOM_R_SUB_NORET; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_inc_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_inc_gu32: - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_G_INC; - } else { - IntNo = AMDILISD::ATOM_G_ADD; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_inc_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_inc_gu32_noret: - isRet = false; - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_G_INC_NORET; - } else { - IntNo = AMDILISD::ATOM_G_ADD_NORET; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_inc_li32: - case AMDGPUIntrinsic::AMDIL_atomic_inc_lu32: - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_L_INC; - } else { - IntNo = AMDILISD::ATOM_L_ADD; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_inc_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_inc_lu32_noret: - isRet = false; - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_L_INC_NORET; - } else { - IntNo = AMDILISD::ATOM_L_ADD_NORET; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_inc_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_inc_ru32: - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_R_INC; - } else { - IntNo = AMDILISD::ATOM_R_ADD; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_inc_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_inc_ru32_noret: - isRet = false; - if (STM->calVersion() >= CAL_VERSION_SC_136) { - IntNo = AMDILISD::ATOM_R_INC_NORET; - } else { - IntNo = AMDILISD::ATOM_R_ADD_NORET; - } - break; - case AMDGPUIntrinsic::AMDIL_atomic_max_gi32: - IntNo = AMDILISD::ATOM_G_MAX; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_gu32: - IntNo = AMDILISD::ATOM_G_UMAX; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_gi32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_MAX_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_UMAX_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_li32: - IntNo = AMDILISD::ATOM_L_MAX; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_lu32: - IntNo = AMDILISD::ATOM_L_UMAX; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_li32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_MAX_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_UMAX_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_ri32: - IntNo = AMDILISD::ATOM_R_MAX; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_ru32: - IntNo = AMDILISD::ATOM_R_UMAX; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_ri32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_MAX_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_max_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_UMAX_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_gi32: - IntNo = AMDILISD::ATOM_G_MIN; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_gu32: - IntNo = AMDILISD::ATOM_G_UMIN; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_gi32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_MIN_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_UMIN_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_li32: - IntNo = AMDILISD::ATOM_L_MIN; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_lu32: - IntNo = AMDILISD::ATOM_L_UMIN; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_li32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_MIN_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_UMIN_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_ri32: - IntNo = AMDILISD::ATOM_R_MIN; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_ru32: - IntNo = AMDILISD::ATOM_R_UMIN; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_ri32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_MIN_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_min_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_UMIN_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_or_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_or_gu32: - IntNo = AMDILISD::ATOM_G_OR; break; - case AMDGPUIntrinsic::AMDIL_atomic_or_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_or_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_OR_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_or_li32: - case AMDGPUIntrinsic::AMDIL_atomic_or_lu32: - IntNo = AMDILISD::ATOM_L_OR; break; - case AMDGPUIntrinsic::AMDIL_atomic_or_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_or_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_OR_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_or_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_or_ru32: - IntNo = AMDILISD::ATOM_R_OR; break; - case AMDGPUIntrinsic::AMDIL_atomic_or_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_or_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_OR_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_sub_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_sub_gu32: - IntNo = AMDILISD::ATOM_G_SUB; break; - case AMDGPUIntrinsic::AMDIL_atomic_sub_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_sub_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_SUB_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_sub_li32: - case AMDGPUIntrinsic::AMDIL_atomic_sub_lu32: - IntNo = AMDILISD::ATOM_L_SUB; break; - case AMDGPUIntrinsic::AMDIL_atomic_sub_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_sub_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_SUB_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_sub_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_sub_ru32: - IntNo = AMDILISD::ATOM_R_SUB; break; - case AMDGPUIntrinsic::AMDIL_atomic_sub_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_sub_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_SUB_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_rsub_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_rsub_gu32: - IntNo = AMDILISD::ATOM_G_RSUB; break; - case AMDGPUIntrinsic::AMDIL_atomic_rsub_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_rsub_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_RSUB_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_rsub_li32: - case AMDGPUIntrinsic::AMDIL_atomic_rsub_lu32: - IntNo = AMDILISD::ATOM_L_RSUB; break; - case AMDGPUIntrinsic::AMDIL_atomic_rsub_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_rsub_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_RSUB_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_rsub_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_rsub_ru32: - IntNo = AMDILISD::ATOM_R_RSUB; break; - case AMDGPUIntrinsic::AMDIL_atomic_rsub_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_rsub_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_RSUB_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_gf32: - bitCastToInt = true; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_xchg_gu32: - IntNo = AMDILISD::ATOM_G_XCHG; break; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_gf32_noret: - bitCastToInt = true; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_xchg_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_XCHG_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_lf32: - bitCastToInt = true; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_li32: - case AMDGPUIntrinsic::AMDIL_atomic_xchg_lu32: - IntNo = AMDILISD::ATOM_L_XCHG; break; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_lf32_noret: - bitCastToInt = true; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_xchg_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_XCHG_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_rf32: - bitCastToInt = true; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_xchg_ru32: - IntNo = AMDILISD::ATOM_R_XCHG; break; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_rf32_noret: - bitCastToInt = true; - case AMDGPUIntrinsic::AMDIL_atomic_xchg_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_xchg_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_XCHG_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_xor_gi32: - case AMDGPUIntrinsic::AMDIL_atomic_xor_gu32: - IntNo = AMDILISD::ATOM_G_XOR; break; - case AMDGPUIntrinsic::AMDIL_atomic_xor_gi32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_xor_gu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_G_XOR_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_xor_li32: - case AMDGPUIntrinsic::AMDIL_atomic_xor_lu32: - IntNo = AMDILISD::ATOM_L_XOR; break; - case AMDGPUIntrinsic::AMDIL_atomic_xor_li32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_xor_lu32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_L_XOR_NORET; break; - case AMDGPUIntrinsic::AMDIL_atomic_xor_ri32: - case AMDGPUIntrinsic::AMDIL_atomic_xor_ru32: - IntNo = AMDILISD::ATOM_R_XOR; break; - case AMDGPUIntrinsic::AMDIL_atomic_xor_ri32_noret: - case AMDGPUIntrinsic::AMDIL_atomic_xor_ru32_noret: - isRet = false; - IntNo = AMDILISD::ATOM_R_XOR_NORET; break; - case AMDGPUIntrinsic::AMDIL_append_alloc_i32: - IntNo = AMDILISD::APPEND_ALLOC; break; - case AMDGPUIntrinsic::AMDIL_append_alloc_i32_noret: - isRet = false; - IntNo = AMDILISD::APPEND_ALLOC_NORET; break; - case AMDGPUIntrinsic::AMDIL_append_consume_i32: - IntNo = AMDILISD::APPEND_CONSUME; break; - case AMDGPUIntrinsic::AMDIL_append_consume_i32_noret: - isRet = false; - IntNo = AMDILISD::APPEND_CONSUME_NORET; break; - }; - - Info.opc = IntNo; - Info.memVT = (bitCastToInt) ? MVT::f32 : MVT::i32; - Info.ptrVal = I.getOperand(0); - Info.offset = 0; - Info.align = 4; - Info.vol = true; - Info.readMem = isRet; - Info.writeMem = true; - return true; + return false; } // The backend supports 32 and 64 bit floating point immediates bool |