diff options
Diffstat (limited to 'src/gallium/drivers/radeon/AMDILISelLowering.cpp')
-rw-r--r-- | src/gallium/drivers/radeon/AMDILISelLowering.cpp | 75 |
1 files changed, 0 insertions, 75 deletions
diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index ca213d1845e..dae63fa2264 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -492,81 +492,6 @@ AMDILTargetLowering::LowerMemArgument( //===----------------------------------------------------------------------===// // Instruction generation functions //===----------------------------------------------------------------------===// -uint32_t -AMDILTargetLowering::addExtensionInstructions( - uint32_t reg, bool signedShift, - unsigned int simpleVT) const -{ - int shiftSize = 0; - uint32_t LShift, RShift; - switch(simpleVT) - { - default: - return reg; - case AMDIL::GPRI8RegClassID: - shiftSize = 24; - LShift = AMDIL::SHL_i8; - if (signedShift) { - RShift = AMDIL::SHR_i8; - } else { - RShift = AMDIL::USHR_i8; - } - break; - case AMDIL::GPRV2I8RegClassID: - shiftSize = 24; - LShift = AMDIL::SHL_v2i8; - if (signedShift) { - RShift = AMDIL::SHR_v2i8; - } else { - RShift = AMDIL::USHR_v2i8; - } - break; - case AMDIL::GPRV4I8RegClassID: - shiftSize = 24; - LShift = AMDIL::SHL_v4i8; - if (signedShift) { - RShift = AMDIL::SHR_v4i8; - } else { - RShift = AMDIL::USHR_v4i8; - } - break; - case AMDIL::GPRI16RegClassID: - shiftSize = 16; - LShift = AMDIL::SHL_i16; - if (signedShift) { - RShift = AMDIL::SHR_i16; - } else { - RShift = AMDIL::USHR_i16; - } - break; - case AMDIL::GPRV2I16RegClassID: - shiftSize = 16; - LShift = AMDIL::SHL_v2i16; - if (signedShift) { - RShift = AMDIL::SHR_v2i16; - } else { - RShift = AMDIL::USHR_v2i16; - } - break; - case AMDIL::GPRV4I16RegClassID: - shiftSize = 16; - LShift = AMDIL::SHL_v4i16; - if (signedShift) { - RShift = AMDIL::SHR_v4i16; - } else { - RShift = AMDIL::USHR_v4i16; - } - break; - }; - uint32_t LoadReg = genVReg(simpleVT); - uint32_t tmp1 = genVReg(simpleVT); - uint32_t tmp2 = genVReg(simpleVT); - generateMachineInst(AMDIL::LOADCONST_i32, LoadReg).addImm(shiftSize); - generateMachineInst(LShift, tmp1, reg, LoadReg); - generateMachineInst(RShift, tmp2, tmp1, LoadReg); - return tmp2; -} - MachineOperand AMDILTargetLowering::convertToReg(MachineOperand op) const { |