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-rw-r--r--src/gallium/drivers/r600/Makefile.am2
-rw-r--r--src/gallium/drivers/r600/eg_asm.c4
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c7
-rw-r--r--src/gallium/drivers/r600/evergreend.h14
-rw-r--r--src/gallium/drivers/r600/r600_asm.c26
-rw-r--r--src/gallium/drivers/r600/r600_asm.h9
-rw-r--r--src/gallium/drivers/r600/r600_llvm.c82
-rw-r--r--src/gallium/drivers/r600/r600_pipe.h2
-rw-r--r--src/gallium/drivers/r600/r600_shader.c82
-rw-r--r--src/gallium/drivers/r600/r600_state.c7
-rw-r--r--src/gallium/drivers/r600/r600_state_common.c4
11 files changed, 167 insertions, 72 deletions
diff --git a/src/gallium/drivers/r600/Makefile.am b/src/gallium/drivers/r600/Makefile.am
index 3089a829e53..77d2674d262 100644
--- a/src/gallium/drivers/r600/Makefile.am
+++ b/src/gallium/drivers/r600/Makefile.am
@@ -29,7 +29,7 @@ libr600_a_SOURCES += \
$(LLVM_C_SOURCES)
libr600_a_LIBADD = \
- $(top_srcdir)/src/gallium/drivers/radeon/libradeon.a
+ $(top_builddir)/src/gallium/drivers/radeon/libradeon.a
AM_CFLAGS += \
$(LLVM_CFLAGS) \
diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
index b6d03ef37de..d2c1679796a 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -133,6 +133,10 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
S_SQ_CF_WORD1_COND(cf->cond) |
S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
break;
+ case CF_NATIVE:
+ bc->bytecode[id++] = cf->isa[0];
+ bc->bytecode[id++] = cf->isa[1];
+ break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
return -EINVAL;
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 517121dc288..81aedb5c0ac 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -796,11 +796,11 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx,
alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
alpha_ref = fui(state->alpha.ref_value);
}
+ dsa->sx_alpha_test_control = alpha_test_control & 0xff;
dsa->alpha_ref = alpha_ref;
/* misc */
db_render_control = 0;
- r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control);
return rstate;
@@ -1428,6 +1428,11 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
blend_bypass = 1;
}
+ if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT)
+ rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
+ else
+ rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
+
color_info |= S_028C70_FORMAT(format) |
S_028C70_COMP_SWAP(swap) |
S_028C70_BLEND_CLAMP(blend_clamp) |
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 4009e91d4fc..105d80f061d 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -32,20 +32,16 @@
#define EVERGREEN_CONTEXT_REG_OFFSET 0X00028000
#define EVERGREEN_CONTEXT_REG_END 0X00029000
#define EVERGREEN_RESOURCE_OFFSET 0x00030000
-#define EVERGREEN_RESOURCE_END 0x00034000
-#define CAYMAN_RESOURCE_END 0x00038000
+#define EVERGREEN_RESOURCE_END 0x00038000
#define EVERGREEN_LOOP_CONST_OFFSET 0x0003A200
-#define EVERGREEN_LOOP_CONST_END 0x0003A26C
+#define EVERGREEN_LOOP_CONST_END 0x0003A500
#define EVERGREEN_BOOL_CONST_OFFSET 0x0003A500
-#define EVERGREEN_BOOL_CONST_END 0x0003A506
-#define CAYMAN_BOOL_CONST_END 0x0003A518
+#define EVERGREEN_BOOL_CONST_END 0x0003A518
#define EVERGREEN_SAMPLER_OFFSET 0X0003C000
-#define EVERGREEN_SAMPLER_END 0X0003CFF0
-#define CAYMAN_SAMPLER_END 0X0003C600
+#define EVERGREEN_SAMPLER_END 0X0003C600
#define EVERGREEN_CTL_CONST_OFFSET 0x0003CFF0
-#define EVERGREEN_CTL_CONST_END 0x0003E200
-#define CAYMAN_CTL_CONST_END 0x0003FF0C
+#define EVERGREEN_CTL_CONST_END 0x0003FF0C
#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
#define EVENT_TYPE_ZPASS_DONE 0x15
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 651933bf37c..5a10bd90776 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -94,6 +94,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
@@ -153,6 +154,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
@@ -171,6 +173,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
@@ -1927,6 +1930,7 @@ int r600_bytecode_build(struct r600_bytecode *bc)
case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
+ case CF_NATIVE:
break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
@@ -2025,13 +2029,12 @@ int r600_bytecode_build(struct r600_bytecode *bc)
}
break;
case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
- if (bc->chip_class == CAYMAN) {
- LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
- r = r600_bytecode_vtx_build(bc, vtx, addr);
- if (r)
- return r;
- addr += 4;
- }
+ LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+ assert(bc->chip_class >= EVERGREEN);
+ r = r600_bytecode_vtx_build(bc, vtx, addr);
+ if (r)
+ return r;
+ addr += 4;
}
LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
r = r600_bytecode_tex_build(bc, tex, addr);
@@ -2069,6 +2072,8 @@ int r600_bytecode_build(struct r600_bytecode *bc)
case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
break;
+ case CF_NATIVE:
+ break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
return -EINVAL;
@@ -2341,6 +2346,10 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
fprintf(stderr, "COND:%X ", cf->cond);
fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
break;
+ case CF_NATIVE:
+ fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
+ fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
+ break;
default:
R600_ERR("Unknown instruction %0x\n", cf->inst);
}
@@ -2477,7 +2486,8 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
if (alu->last) {
for (i = 0; i < nliteral; i++, id++) {
float *f = (float*)(bc->bytecode + id);
- fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
+ fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
+ *(bc->bytecode + id));
}
id += nliteral & 1;
nliteral = 0;
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 5790ead991f..a8a157b79e4 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -135,6 +135,14 @@ struct r600_bytecode_kcache {
unsigned addr;
};
+/* A value of CF_NATIVE in r600_bytecode_cf::inst means that this instruction
+ * has already been encoded, and the encoding has been stored in
+ * r600_bytecode::isa. This is used by the LLVM backend to emit CF instructions
+ * e.g. RAT_WRITE_* that can't be properly represented by struct
+ * r600_bytecode_cf.
+ */
+#define CF_NATIVE ~0
+
struct r600_bytecode_cf {
struct list_head list;
@@ -157,6 +165,7 @@ struct r600_bytecode_cf {
struct r600_bytecode_alu *curr_bs_head;
struct r600_bytecode_alu *prev_bs_head;
struct r600_bytecode_alu *prev2_bs_head;
+ unsigned isa[2];
};
#define FC_NONE 0
diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm.c
index d467baf60fb..f916604db7b 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -21,10 +21,44 @@ static LLVMValueRef llvm_fetch_const(
enum tgsi_opcode_type type,
unsigned swizzle)
{
- return lp_build_intrinsic_unary(bld_base->base.gallivm->builder,
+ LLVMValueRef cval = lp_build_intrinsic_unary(bld_base->base.gallivm->builder,
"llvm.AMDGPU.load.const", bld_base->base.elem_type,
lp_build_const_int32(bld_base->base.gallivm,
radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)));
+
+ return bitcast(bld_base, type, cval);
+}
+
+static void llvm_load_system_value(
+ struct radeon_llvm_context * ctx,
+ unsigned index,
+ const struct tgsi_full_declaration *decl)
+{
+ unsigned chan;
+
+ switch (decl->Semantic.Name) {
+ case TGSI_SEMANTIC_INSTANCEID: chan = 3; break;
+ case TGSI_SEMANTIC_VERTEXID: chan = 0; break;
+ default: assert(!"unknown system value");
+ }
+
+ LLVMValueRef reg = lp_build_const_int32(
+ ctx->soa.bld_base.base.gallivm, chan);
+ ctx->system_values[index] = lp_build_intrinsic_unary(
+ ctx->soa.bld_base.base.gallivm->builder,
+ "llvm.R600.load.input",
+ ctx->soa.bld_base.base.elem_type, reg);
+}
+
+static LLVMValueRef llvm_fetch_system_value(
+ struct lp_build_tgsi_context * bld_base,
+ const struct tgsi_full_src_register *reg,
+ enum tgsi_opcode_type type,
+ unsigned swizzle)
+{
+ struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
+ LLVMValueRef cval = ctx->system_values[reg->Register.Index];
+ return bitcast(bld_base, type, cval);
}
static void llvm_load_input(
@@ -59,17 +93,13 @@ static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
for (i = 0; i < ctx->reserved_reg_count; i++) {
unsigned chan;
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
- LLVMValueRef reg;
LLVMValueRef reg_index = lp_build_const_int32(
base->gallivm,
radeon_llvm_reg_index_soa(i, chan));
- reg = lp_build_intrinsic_unary(base->gallivm->builder,
- "llvm.AMDGPU.reserve.reg",
- base->elem_type, reg_index);
lp_build_intrinsic_unary(base->gallivm->builder,
- "llvm.AMDGPU.export.reg",
+ "llvm.AMDGPU.reserve.reg",
LLVMVoidTypeInContext(base->gallivm->context),
- reg);
+ reg_index);
}
}
}
@@ -85,7 +115,6 @@ static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
unsigned chan;
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
LLVMValueRef output;
- LLVMValueRef store_output;
unsigned adjusted_reg_idx = i +
ctx->reserved_reg_count;
LLVMValueRef reg_index = lp_build_const_int32(
@@ -95,16 +124,11 @@ static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
output = LLVMBuildLoad(base->gallivm->builder,
ctx->soa.outputs[i][chan], "");
- store_output = lp_build_intrinsic_binary(
+ lp_build_intrinsic_binary(
base->gallivm->builder,
"llvm.AMDGPU.store.output",
- base->elem_type,
- output, reg_index);
-
- lp_build_intrinsic_unary(base->gallivm->builder,
- "llvm.AMDGPU.export.reg",
LLVMVoidTypeInContext(base->gallivm->context),
- store_output);
+ output, reg_index);
}
}
}
@@ -169,28 +193,7 @@ static struct lp_build_tgsi_action dot_action = {
.intr_name = "llvm.AMDGPU.dp4"
};
-static void txp_fetch_args(
- struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
-{
- LLVMValueRef src_w;
- unsigned chan;
- LLVMValueRef coords[4];
-
- emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
- src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
- for (chan = 0; chan < 3; chan++ ) {
- LLVMValueRef arg = lp_build_emit_fetch(bld_base,
- emit_data->inst, 0, chan);
- coords[chan] = lp_build_emit_llvm_binary(bld_base,
- TGSI_OPCODE_DIV, arg, src_w);
- }
- coords[3] = bld_base->base.one;
- emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
- coords, 4);
- emit_data->arg_count = 1;
-}
LLVMModuleRef r600_tgsi_llvm(
struct radeon_llvm_context * ctx,
@@ -204,20 +207,25 @@ LLVMModuleRef r600_tgsi_llvm(
bld_base->info = &shader_info;
bld_base->userdata = ctx;
bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = llvm_fetch_const;
+ bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = llvm_fetch_system_value;
bld_base->emit_prologue = llvm_emit_prologue;
bld_base->emit_epilogue = llvm_emit_epilogue;
ctx->userdata = ctx;
ctx->load_input = llvm_load_input;
+ ctx->load_system_value = llvm_load_system_value;
bld_base->op_actions[TGSI_OPCODE_DP2] = dot_action;
bld_base->op_actions[TGSI_OPCODE_DP3] = dot_action;
bld_base->op_actions[TGSI_OPCODE_DP4] = dot_action;
bld_base->op_actions[TGSI_OPCODE_DPH] = dot_action;
+ bld_base->op_actions[TGSI_OPCODE_DDX].emit = llvm_emit_tex;
+ bld_base->op_actions[TGSI_OPCODE_DDY].emit = llvm_emit_tex;
bld_base->op_actions[TGSI_OPCODE_TEX].emit = llvm_emit_tex;
bld_base->op_actions[TGSI_OPCODE_TXB].emit = llvm_emit_tex;
bld_base->op_actions[TGSI_OPCODE_TXD].emit = llvm_emit_tex;
bld_base->op_actions[TGSI_OPCODE_TXL].emit = llvm_emit_tex;
- bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
+ bld_base->op_actions[TGSI_OPCODE_TXF].emit = llvm_emit_tex;
+ bld_base->op_actions[TGSI_OPCODE_TXQ].emit = llvm_emit_tex;
bld_base->op_actions[TGSI_OPCODE_TXP].emit = llvm_emit_tex;
lp_build_tgsi_llvm(bld_base, tokens);
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 63fc27564d7..db455f021ad 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -161,6 +161,7 @@ struct r600_pipe_dsa {
ubyte valuemask[2];
ubyte writemask[2];
bool is_flush;
+ unsigned sx_alpha_test_control;
};
struct r600_vertex_element
@@ -250,6 +251,7 @@ struct r600_context {
struct pipe_framebuffer_state framebuffer;
unsigned cb_target_mask;
unsigned fb_cb_shader_mask;
+ unsigned sx_alpha_test_control;
unsigned cb_shader_mask;
unsigned cb_color_control;
unsigned pa_sc_line_stipple;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 5e22b35ba48..cd78104a010 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -287,6 +287,7 @@ static void llvm_if(struct r600_shader_ctx *ctx, struct r600_bytecode_alu * alu,
{
alu->inst = pred_inst;
alu->predicate = 1;
+ alu->dst.write = 0;
alu->src[1].sel = V_SQ_ALU_SRC_0;
alu->src[1].chan = 0;
alu->last = 1;
@@ -362,6 +363,10 @@ static unsigned r600_fc_from_byte_stream(struct r600_shader_ctx *ctx,
tgsi_loop_brk_cont(ctx);
}
break;
+ case 8:
+ r600_break_from_byte_stream(ctx, &alu,
+ CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT));
+ break;
}
return bytes_read;
@@ -401,10 +406,43 @@ static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx *ctx,
return bytes_read;
}
+static int r600_vtx_from_byte_stream(struct r600_shader_ctx *ctx,
+ unsigned char * bytes, unsigned bytes_read)
+{
+ struct r600_bytecode_vtx vtx;
+ memset(&vtx, 0, sizeof(vtx));
+ vtx.inst = bytes[bytes_read++];
+ vtx.fetch_type = bytes[bytes_read++];
+ vtx.buffer_id = bytes[bytes_read++];
+ vtx.src_gpr = bytes[bytes_read++];
+ vtx.src_sel_x = bytes[bytes_read++];
+ vtx.mega_fetch_count = bytes[bytes_read++];
+ vtx.dst_gpr = bytes[bytes_read++];
+ vtx.dst_sel_x = bytes[bytes_read++];
+ vtx.dst_sel_y = bytes[bytes_read++];
+ vtx.dst_sel_z = bytes[bytes_read++];
+ vtx.dst_sel_w = bytes[bytes_read++];
+ vtx.use_const_fields = bytes[bytes_read++];
+ vtx.data_format = bytes[bytes_read++];
+ vtx.num_format_all = bytes[bytes_read++];
+ vtx.format_comp_all = bytes[bytes_read++];
+ vtx.srf_mode_all = bytes[bytes_read++];
+ vtx.offset = bytes[bytes_read++];
+ vtx.endian = bytes[bytes_read++];
+
+ if (r600_bytecode_add_vtx(ctx->bc, &vtx)) {
+ fprintf(stderr, "Error adding vtx\n");
+ }
+ /* Use the Texture Cache */
+ ctx->bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX;
+ return bytes_read;
+}
+
static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
unsigned char * bytes, unsigned num_bytes)
{
unsigned bytes_read = 0;
+ unsigned i, byte;
while (bytes_read < num_bytes) {
char inst_type = bytes[bytes_read++];
switch (inst_type) {
@@ -420,6 +458,20 @@ static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
bytes_read = r600_fc_from_byte_stream(ctx, bytes,
bytes_read);
break;
+ case 3:
+ r600_bytecode_add_cfinst(ctx->bc, CF_NATIVE);
+ for (i = 0; i < 2; i++) {
+ for (byte = 0 ; byte < 4; byte++) {
+ ctx->bc->cf_last->isa[i] |=
+ (bytes[bytes_read++] << (byte * 8));
+ }
+ }
+ break;
+
+ case 4:
+ bytes_read = r600_vtx_from_byte_stream(ctx, bytes,
+ bytes_read);
+ break;
default:
/* XXX: Error here */
break;
@@ -670,8 +722,8 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
ctx->shader->input[i].name = d->Semantic.Name;
ctx->shader->input[i].sid = d->Semantic.Index;
ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
- ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
- ctx->shader->input[i].centroid = d->Declaration.Centroid;
+ ctx->shader->input[i].interpolate = d->Interp.Interpolate;
+ ctx->shader->input[i].centroid = d->Interp.Centroid;
ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
switch (ctx->shader->input[i].name) {
@@ -697,7 +749,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
ctx->shader->output[i].sid = d->Semantic.Index;
ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
- ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
+ ctx->shader->output[i].interpolate = d->Interp.Interpolate;
ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
if (ctx->type == TGSI_PROCESSOR_VERTEX) {
switch (d->Semantic.Name) {
@@ -5102,7 +5154,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
{80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
- {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+ {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
{TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
{TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
{TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
@@ -5168,16 +5220,16 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
{TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
- {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
- {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
- {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_UARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
@@ -5276,7 +5328,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
{80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
- {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+ {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
{TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
{TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
{TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
@@ -5342,16 +5394,16 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
{TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
- {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
- {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
- {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
@@ -5450,7 +5502,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
{80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
- {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+ {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
{TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2},
{TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
{TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
@@ -5516,16 +5568,16 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
{TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
{TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
- {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
- {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
- {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 3a83b613e58..acf59f80bf4 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -805,9 +805,9 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
alpha_ref = fui(state->alpha.ref_value);
}
+ dsa->sx_alpha_test_control = alpha_test_control & 0xff;
dsa->alpha_ref = alpha_ref;
- r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
return rstate;
}
@@ -1466,6 +1466,11 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
blend_bypass = 1;
}
+ if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT)
+ rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
+ else
+ rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
+
color_info |= S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_BYPASS(blend_bypass) |
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index ccae7d91d43..d47383558d9 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -244,6 +244,8 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
return;
rstate = &dsa->rstate;
rctx->states[rstate->id] = rstate;
+ rctx->sx_alpha_test_control &= ~0xff;
+ rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
rctx->alpha_ref = dsa->alpha_ref;
rctx->alpha_ref_dirty = true;
r600_context_pipe_state_set(rctx, rstate);
@@ -796,6 +798,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
@@ -817,6 +820,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
+ r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 22:53:02 +0000