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-rw-r--r--src/gallium/drivers/r600/evergreen_hw_context.c14
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c36
-rw-r--r--src/gallium/drivers/r600/r600_hw_context.c2
-rw-r--r--src/gallium/drivers/r600/r600_pipe.h9
-rw-r--r--src/gallium/drivers/r600/r600_state_common.c1
5 files changed, 46 insertions, 16 deletions
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index 352aeb8b4a1..161709cc233 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -829,18 +829,16 @@ void evergreen_flush_vgt_streamout(struct r600_context *ctx)
void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
{
struct radeon_winsys_cs *cs = ctx->cs;
+ bool enable = buffer_enable_bit != 0;
- if (buffer_enable_bit) {
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
+ if (enable != ctx->atom_eg_strmout_config.stream0_enable) {
+ ctx->atom_eg_strmout_config.stream0_enable = enable;
+ r600_emit_atom(ctx, &ctx->atom_eg_strmout_config.atom);
+ }
+ if (buffer_enable_bit) {
cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
- } else {
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
}
}
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 65becc41b9f..adc400f1e79 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -781,6 +781,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
prov_vtx = 0;
rstate = &rs->rstate;
+ rs->rasterizer_discard = state->rasterizer_discard;
rs->flatshade = state->flatshade;
rs->sprite_coord_enable = state->sprite_coord_enable;
rs->two_side = state->light_twoside;
@@ -849,8 +850,8 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
S_028814_PROVOKING_VTX_LAST(prov_vtx) |
- S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
- S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+ S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
+ S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
S_028814_FACE(!state->front_ccw) |
S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
@@ -862,6 +863,16 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
return rstate;
}
+void evergreen_set_rasterizer_discard(struct pipe_context *ctx, boolean discard)
+{
+ struct r600_context *rctx = (struct r600_context*)ctx;
+
+ if (discard != rctx->atom_eg_strmout_config.rasterizer_discard) {
+ rctx->atom_eg_strmout_config.rasterizer_discard = discard;
+ r600_atom_dirty(rctx, &rctx->atom_eg_strmout_config.atom);
+ }
+}
+
static void *evergreen_create_sampler_state(struct pipe_context *ctx,
const struct pipe_sampler_state *state)
{
@@ -1676,9 +1687,22 @@ static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_
r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
}
+static void evergreen_emit_streamout_config(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_atom_eg_strmout_config *a = (struct r600_atom_eg_strmout_config*)atom;
+
+ r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG,
+ S_028B94_STREAMOUT_0_EN(a->stream0_enable) |
+ S_028B94_RAST_STREAM(a->rasterizer_discard ? 4 : 0));
+}
+
void evergreen_init_state_functions(struct r600_context *rctx)
{
r600_init_atom(&rctx->atom_db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
+ r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom);
+ r600_init_atom(&rctx->atom_eg_strmout_config.atom, evergreen_emit_streamout_config, 6, 0);
+ r600_atom_dirty(rctx, &rctx->atom_eg_strmout_config.atom);
rctx->context.create_blend_state = evergreen_create_blend_state;
rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
@@ -1763,9 +1787,7 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
- r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
- r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
- r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
+ r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
@@ -2258,9 +2280,7 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
- r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
- r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
- r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
+ r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 6d30aa3ca05..1dc23fdcca5 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1270,6 +1270,8 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
r600_emit_atom(ctx, &ctx->atom_start_cs.atom);
r600_atom_dirty(ctx, &ctx->atom_db_misc_state.atom);
+ if (ctx->chip_class >= EVERGREEN)
+ r600_atom_dirty(ctx, &ctx->atom_eg_strmout_config.atom);
if (streamout_suspended) {
ctx->streamout_start = TRUE;
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 9550e9e0bae..de73bd8ee68 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -86,6 +86,12 @@ struct r600_atom_db_misc_state {
bool flush_depthstencil_enabled;
};
+struct r600_atom_eg_strmout_config {
+ struct r600_atom atom;
+ bool rasterizer_discard;
+ bool stream0_enable;
+};
+
enum r600_pipe_state_id {
R600_PIPE_STATE_BLEND = 0,
R600_PIPE_STATE_BLEND_COLOR,
@@ -153,6 +159,7 @@ struct r600_pipe_rasterizer {
float offset_units;
float offset_scale;
bool scissor_enable;
+ bool rasterizer_discard;
};
struct r600_pipe_blend {
@@ -294,6 +301,7 @@ struct r600_context {
struct r600_atom_surface_sync atom_surface_sync;
struct r600_atom atom_r6xx_flush_and_inv;
struct r600_atom_db_misc_state atom_db_misc_state;
+ struct r600_atom_eg_strmout_config atom_eg_strmout_config;
/* Below are variables from the old r600_context.
*/
@@ -384,6 +392,7 @@ boolean evergreen_is_format_supported(struct pipe_screen *screen,
enum pipe_texture_target target,
unsigned sample_count,
unsigned usage);
+void evergreen_set_rasterizer_discard(struct pipe_context *ctx, boolean discard);
/* r600_blit.c */
void r600_init_blit_functions(struct r600_context *rctx);
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 565af35c7e5..2f643cf0acd 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -301,6 +301,7 @@ void r600_bind_rs_state(struct pipe_context *ctx, void *state)
if (rctx->chip_class >= EVERGREEN) {
evergreen_polygon_offset_update(rctx);
+ evergreen_set_rasterizer_discard(ctx, rs->rasterizer_discard);
} else {
r600_polygon_offset_update(rctx);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 22:14:16 +0000