diff options
Diffstat (limited to 'src/gallium/drivers/r600')
-rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 10 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_pipe.c | 123 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_pipe.h | 7 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_texture.c | 5 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_uvd.c | 2 |
5 files changed, 12 insertions, 135 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 754c265c8c5..83cb02410df 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1195,7 +1195,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, if (util_format_get_blocksize(pipe_format) >= 16) non_disp_tiling = 1; } - nbanks = eg_num_banks(rscreen->tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); if (texture->target == PIPE_TEXTURE_1D_ARRAY) { height = 1; @@ -1348,7 +1348,7 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx, unsigned block_size = align(util_format_get_blocksize(pipe_buffer->format), 4); unsigned pitch_alignment = - MAX2(64, rctx->screen->tiling_info.group_bytes / block_size); + MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size); unsigned pitch = align(pipe_buffer->width0, pitch_alignment); /* XXX: This is copied from evergreen_init_color_surface(). I don't @@ -1456,7 +1456,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, if (util_format_get_blocksize(surf->base.format) >= 16) non_disp_tiling = 1; } - nbanks = eg_num_banks(rscreen->tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); desc = util_format_description(surf->base.format); for (i = 0; i < 4; i++) { if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { @@ -1628,7 +1628,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, macro_aspect = eg_macro_tile_aspect(macro_aspect); bankw = eg_bank_wh(bankw); bankh = eg_bank_wh(bankh); - nbanks = eg_num_banks(rscreen->tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); offset >>= 8; surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) | @@ -3655,7 +3655,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, sub_cmd = 0x8; lbpp = util_logbase2(bpp); pitch_tile_max = ((pitch / bpp) >> 3) - 1; - nbanks = eg_num_banks(rctx->screen->tiling_info.num_banks); + nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks); if (dst_mode == RADEON_SURF_MODE_LINEAR) { /* T2L */ diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index fd5c2a8e0ff..87581b42e24 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -32,7 +32,6 @@ #include "pipe/p_shader_tokens.h" #include "util/u_blitter.h" #include "util/u_debug.h" -#include "util/u_format_s3tc.h" #include "util/u_memory.h" #include "util/u_simple_shaders.h" #include "util/u_upload_mgr.h" @@ -1048,116 +1047,6 @@ static boolean r600_fence_finish(struct pipe_screen *pscreen, return rscreen->fences.data[rfence->index] != 0; } -static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) -{ - switch ((tiling_config & 0xe) >> 1) { - case 0: - rscreen->tiling_info.num_channels = 1; - break; - case 1: - rscreen->tiling_info.num_channels = 2; - break; - case 2: - rscreen->tiling_info.num_channels = 4; - break; - case 3: - rscreen->tiling_info.num_channels = 8; - break; - default: - return -EINVAL; - } - - switch ((tiling_config & 0x30) >> 4) { - case 0: - rscreen->tiling_info.num_banks = 4; - break; - case 1: - rscreen->tiling_info.num_banks = 8; - break; - default: - return -EINVAL; - - } - switch ((tiling_config & 0xc0) >> 6) { - case 0: - rscreen->tiling_info.group_bytes = 256; - break; - case 1: - rscreen->tiling_info.group_bytes = 512; - break; - default: - return -EINVAL; - } - return 0; -} - -static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) -{ - switch (tiling_config & 0xf) { - case 0: - rscreen->tiling_info.num_channels = 1; - break; - case 1: - rscreen->tiling_info.num_channels = 2; - break; - case 2: - rscreen->tiling_info.num_channels = 4; - break; - case 3: - rscreen->tiling_info.num_channels = 8; - break; - default: - return -EINVAL; - } - - switch ((tiling_config & 0xf0) >> 4) { - case 0: - rscreen->tiling_info.num_banks = 4; - break; - case 1: - rscreen->tiling_info.num_banks = 8; - break; - case 2: - rscreen->tiling_info.num_banks = 16; - break; - default: - return -EINVAL; - } - - switch ((tiling_config & 0xf00) >> 8) { - case 0: - rscreen->tiling_info.group_bytes = 256; - break; - case 1: - rscreen->tiling_info.group_bytes = 512; - break; - default: - return -EINVAL; - } - return 0; -} - -static int r600_init_tiling(struct r600_screen *rscreen) -{ - uint32_t tiling_config = rscreen->b.info.r600_tiling_config; - - /* set default group bytes, overridden by tiling info ioctl */ - if (rscreen->b.chip_class <= R700) { - rscreen->tiling_info.group_bytes = 256; - } else { - rscreen->tiling_info.group_bytes = 512; - } - - if (!tiling_config) - return 0; - - if (rscreen->b.chip_class <= R700) { - return r600_interpret_tiling(rscreen, tiling_config); - } else { - return evergreen_interpret_tiling(rscreen, tiling_config); - } -} - static uint64_t r600_get_timestamp(struct pipe_screen *screen) { struct r600_screen *rscreen = (struct r600_screen*)screen; @@ -1224,7 +1113,10 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) } r600_init_screen_resource_functions(&rscreen->b.b); - r600_common_screen_init(&rscreen->b, ws); + if (!r600_common_screen_init(&rscreen->b, ws)) { + FREE(rscreen); + return NULL; + } rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0); if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE)) @@ -1288,13 +1180,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) rscreen->has_cp_dma = rscreen->b.info.drm_minor >= 27 && !(rscreen->b.debug_flags & DBG_NO_CP_DMA); - if (r600_init_tiling(rscreen)) { - FREE(rscreen); - return NULL; - } - - util_format_s3tc_init(); - rscreen->fences.bo = NULL; rscreen->fences.data = NULL; rscreen->fences.next_index = 0; diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 7927e2d9858..80a96ca71d4 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -218,19 +218,12 @@ struct r600_pipe_fences { #define DBG_SB_DISASM (1 << 27) #define DBG_SB_SAFEMATH (1 << 28) -struct r600_tiling_info { - unsigned num_channels; - unsigned num_banks; - unsigned group_bytes; -}; - struct r600_screen { struct r600_common_screen b; bool has_streamout; bool has_msaa; bool has_cp_dma; bool has_compressed_msaa_texturing; - struct r600_tiling_info tiling_info; struct r600_pipe_fences fences; /*for compute global memory binding, we allocate stuff here, instead of diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 403efd1a2ae..481c6543923 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -29,7 +29,6 @@ #include "r600d.h" #include <errno.h> -#include "util/u_format_s3tc.h" #include "util/u_memory.h" @@ -372,8 +371,8 @@ void r600_texture_get_cmask_info(struct r600_screen *rscreen, unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height; unsigned element_bits = 4; unsigned cmask_cache_bits = 1024; - unsigned num_pipes = rscreen->tiling_info.num_channels; - unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes; + unsigned num_pipes = rscreen->b.tiling_info.num_channels; + unsigned pipe_interleave_bytes = rscreen->b.tiling_info.group_bytes; unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes; unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements; diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c index 00669fd3171..05d2ad07514 100644 --- a/src/gallium/drivers/r600/r600_uvd.c +++ b/src/gallium/drivers/r600/r600_uvd.c @@ -156,7 +156,7 @@ static struct radeon_winsys_cs_handle* r600_uvd_set_dtb(struct ruvd_msg *msg, st struct r600_texture *chroma = (struct r600_texture *)buf->resources[1]; msg->body.decode.dt_field_mode = buf->base.interlaced; - msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->tiling_info.num_banks)); + msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.tiling_info.num_banks)); ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface); 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