diff options
Diffstat (limited to 'src/gallium/drivers/r600')
-rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 7 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_pipe.h | 2 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 7 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_state_common.c | 4 |
4 files changed, 18 insertions, 2 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 97a27d242c0..82313ea6031 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -796,11 +796,11 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx, alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); alpha_ref = fui(state->alpha.ref_value); } + dsa->sx_alpha_test_control = alpha_test_control & 0xff; dsa->alpha_ref = alpha_ref; /* misc */ db_render_control = 0; - r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control); r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control); r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control); return rstate; @@ -1428,6 +1428,11 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta blend_bypass = 1; } + if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) + rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1); + else + rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS; + color_info |= S_028C70_FORMAT(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) | diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index e17011bfb68..3a5f5509b62 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -161,6 +161,7 @@ struct r600_pipe_dsa { ubyte valuemask[2]; ubyte writemask[2]; bool is_flush; + unsigned sx_alpha_test_control; }; struct r600_vertex_element @@ -257,6 +258,7 @@ struct r600_context { struct pipe_framebuffer_state framebuffer; unsigned cb_target_mask; unsigned fb_cb_shader_mask; + unsigned sx_alpha_test_control; unsigned cb_shader_mask; unsigned cb_color_control; unsigned pa_sc_line_stipple; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 116ec5fca0e..2ad57b27f10 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -805,9 +805,9 @@ static void *r600_create_dsa_state(struct pipe_context *ctx, alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); alpha_ref = fui(state->alpha.ref_value); } + dsa->sx_alpha_test_control = alpha_test_control & 0xff; dsa->alpha_ref = alpha_ref; - r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control); r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control); return rstate; } @@ -1466,6 +1466,11 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, blend_bypass = 1; } + if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT) + rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1); + else + rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS; + color_info |= S_0280A0_FORMAT(format) | S_0280A0_COMP_SWAP(swap) | S_0280A0_BLEND_BYPASS(blend_bypass) | diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 02577ef61a2..a817831fd82 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -244,6 +244,8 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state) return; rstate = &dsa->rstate; rctx->states[rstate->id] = rstate; + rctx->sx_alpha_test_control &= ~0xff; + rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control; rctx->alpha_ref = dsa->alpha_ref; rctx->alpha_ref_dirty = true; r600_context_pipe_state_set(rctx, rstate); @@ -796,6 +798,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0); r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias); r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index); + r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0); r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart); r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance); r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0); @@ -817,6 +820,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask); r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias); r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index); + r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control); r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart); r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance); |