diff options
Diffstat (limited to 'src/gallium/drivers/r600/radeon.h')
| -rw-r--r-- | src/gallium/drivers/r600/radeon.h | 198 |
1 files changed, 92 insertions, 106 deletions
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h index 8f00a4895a0..aaac8de5283 100644 --- a/src/gallium/drivers/r600/radeon.h +++ b/src/gallium/drivers/r600/radeon.h @@ -77,6 +77,14 @@ enum radeon_family { CHIP_LAST, }; +enum { + R600_SHADER_PS = 1, + R600_SHADER_VS, + R600_SHADER_GS, + R600_SHADER_FS, + R600_SHADER_MAX = R600_SHADER_FS, +}; + enum radeon_family radeon_get_family(struct radeon *rw); /* @@ -98,22 +106,23 @@ struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo); struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo); int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo); +struct radeon_stype_info; /* * states functions */ struct radeon_state { struct radeon *radeon; unsigned refcount; - unsigned type; + struct radeon_stype_info *stype; + unsigned state_id; unsigned id; + unsigned shader_index; unsigned nstates; - u32 *states; + u32 states[64]; unsigned npm4; unsigned cpm4; u32 pm4_crc; - u32 *pm4; - u32 nimmd; - u32 *immd; + u32 pm4[128]; unsigned nbo; struct radeon_bo *bo[4]; unsigned nreloc; @@ -123,38 +132,22 @@ struct radeon_state { unsigned bo_dirty[4]; }; -struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id); -struct radeon_state *radeon_state_incref(struct radeon_state *state); -struct radeon_state *radeon_state_decref(struct radeon_state *state); +int radeon_state_init(struct radeon_state *rstate, struct radeon *radeon, u32 type, u32 id, u32 shader_class); +void radeon_state_fini(struct radeon_state *state); int radeon_state_pm4(struct radeon_state *state); +int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type); /* * draw functions */ struct radeon_draw { - unsigned refcount; struct radeon *radeon; - unsigned nstate; struct radeon_state **state; - unsigned cpm4; }; -struct radeon_draw *radeon_draw(struct radeon *radeon); -struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw); -struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw); -struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw); -int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state); -int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state); -int radeon_draw_check(struct radeon_draw *draw); - -struct radeon_ctx *radeon_ctx(struct radeon *radeon); -struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx); -struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx); -int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw); -int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw); -int radeon_ctx_pm4(struct radeon_ctx *ctx); -int radeon_ctx_submit(struct radeon_ctx *ctx); -void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file); +int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon); +void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state); +void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state); /* * radeon context functions @@ -169,95 +162,57 @@ struct radeon_cs_reloc { #pragma pack() struct radeon_ctx { - int refcount; struct radeon *radeon; u32 *pm4; - u32 cpm4; - u32 draw_cpm4; - unsigned id; - unsigned next_id; + int cdwords; + int ndwords; unsigned nreloc; struct radeon_cs_reloc *reloc; unsigned nbo; struct radeon_bo **bo; - unsigned ndraw; - struct radeon_draw *cdraw; - struct radeon_draw **draw; - unsigned nstate; - struct radeon_state **state; }; +int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon); +void radeon_ctx_fini(struct radeon_ctx *ctx); +void radeon_ctx_clear(struct radeon_ctx *ctx); +int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw); +int radeon_ctx_submit(struct radeon_ctx *ctx); +void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file); +int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state); + /* * R600/R700 */ -#define R600_NSTATE 1280 -#define R600_NTYPE 32 +enum r600_stype { + R600_STATE_CONFIG, + R600_STATE_CB_CNTL, + R600_STATE_RASTERIZER, + R600_STATE_VIEWPORT, + R600_STATE_SCISSOR, + R600_STATE_BLEND, + R600_STATE_DSA, + R600_STATE_SHADER, /* has PS,VS,GS,FS variants */ + R600_STATE_CONSTANT, /* has PS,VS,GS,FS variants */ + R600_STATE_RESOURCE, /* has PS,VS,GS,FS variants */ + R600_STATE_SAMPLER, /* has PS,VS,GS,FS variants */ + R600_STATE_SAMPLER_BORDER, /* has PS,VS,GS,FS variants */ + R600_STATE_CB0, + R600_STATE_CB1, + R600_STATE_CB2, + R600_STATE_CB3, + R600_STATE_CB4, + R600_STATE_CB5, + R600_STATE_CB6, + R600_STATE_CB7, + R600_STATE_DB, + R600_STATE_QUERY_BEGIN, + R600_STATE_QUERY_END, + R600_STATE_UCP, + R600_STATE_VGT, + R600_STATE_DRAW, +}; -#define R600_CONFIG 0 -#define R600_CONFIG_TYPE 0 -#define R600_CB_CNTL 1 -#define R600_CB_CNTL_TYPE 1 -#define R600_RASTERIZER 2 -#define R600_RASTERIZER_TYPE 2 -#define R600_VIEWPORT 3 -#define R600_VIEWPORT_TYPE 3 -#define R600_SCISSOR 4 -#define R600_SCISSOR_TYPE 4 -#define R600_BLEND 5 -#define R600_BLEND_TYPE 5 -#define R600_DSA 6 -#define R600_DSA_TYPE 6 -#define R600_VS_SHADER 7 -#define R600_VS_SHADER_TYPE 7 -#define R600_PS_SHADER 8 -#define R600_PS_SHADER_TYPE 8 -#define R600_PS_CONSTANT 9 -#define R600_PS_CONSTANT_TYPE 9 -#define R600_VS_CONSTANT 265 -#define R600_VS_CONSTANT_TYPE 10 -#define R600_PS_RESOURCE 521 -#define R600_PS_RESOURCE_TYPE 11 -#define R600_VS_RESOURCE 681 -#define R600_VS_RESOURCE_TYPE 12 -#define R600_FS_RESOURCE 841 -#define R600_FS_RESOURCE_TYPE 13 -#define R600_GS_RESOURCE 1001 -#define R600_GS_RESOURCE_TYPE 14 -#define R600_PS_SAMPLER 1161 -#define R600_PS_SAMPLER_TYPE 15 -#define R600_VS_SAMPLER 1179 -#define R600_VS_SAMPLER_TYPE 16 -#define R600_GS_SAMPLER 1197 -#define R600_GS_SAMPLER_TYPE 17 -#define R600_PS_SAMPLER_BORDER 1215 -#define R600_PS_SAMPLER_BORDER_TYPE 18 -#define R600_VS_SAMPLER_BORDER 1233 -#define R600_VS_SAMPLER_BORDER_TYPE 19 -#define R600_GS_SAMPLER_BORDER 1251 -#define R600_GS_SAMPLER_BORDER_TYPE 20 -#define R600_CB0 1269 -#define R600_CB0_TYPE 21 -#define R600_CB1 1270 -#define R600_CB1_TYPE 22 -#define R600_CB2 1271 -#define R600_CB2_TYPE 23 -#define R600_CB3 1272 -#define R600_CB3_TYPE 24 -#define R600_CB4 1273 -#define R600_CB4_TYPE 25 -#define R600_CB5 1274 -#define R600_CB5_TYPE 26 -#define R600_CB6 1275 -#define R600_CB6_TYPE 27 -#define R600_CB7 1276 -#define R600_CB7_TYPE 28 -#define R600_DB 1277 -#define R600_DB_TYPE 29 -#define R600_VGT 1278 -#define R600_VGT_TYPE 30 -#define R600_DRAW 1279 -#define R600_DRAW_TYPE 31 /* R600_CONFIG */ #define R600_CONFIG__SQ_CONFIG 0 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1 @@ -639,9 +594,40 @@ struct radeon_ctx { /* R600_DRAW */ #define R600_DRAW__VGT_NUM_INDICES 0 #define R600_DRAW__VGT_DMA_BASE_HI 1 -#define R600_DRAW__VGT_DMA_BASE 2 +#define R600_DRAW__VGT_DMA_BASE 2 #define R600_DRAW__VGT_DRAW_INITIATOR 3 -#define R600_DRAW_SIZE 4 -#define R600_DRAW_PM4 128 +#define R600_DRAW_SIZE 4 +#define R600_DRAW_PM4 128 +/* R600_CLIP */ +#define R600_CLIP__PA_CL_UCP_X_0 0 +#define R600_CLIP__PA_CL_UCP_Y_0 1 +#define R600_CLIP__PA_CL_UCP_Z_0 2 +#define R600_CLIP__PA_CL_UCP_W_0 3 +#define R600_CLIP__PA_CL_UCP_X_1 4 +#define R600_CLIP__PA_CL_UCP_Y_1 5 +#define R600_CLIP__PA_CL_UCP_Z_1 6 +#define R600_CLIP__PA_CL_UCP_W_1 7 +#define R600_CLIP__PA_CL_UCP_X_2 8 +#define R600_CLIP__PA_CL_UCP_Y_2 9 +#define R600_CLIP__PA_CL_UCP_Z_2 10 +#define R600_CLIP__PA_CL_UCP_W_2 11 +#define R600_CLIP__PA_CL_UCP_X_3 12 +#define R600_CLIP__PA_CL_UCP_Y_3 13 +#define R600_CLIP__PA_CL_UCP_Z_3 14 +#define R600_CLIP__PA_CL_UCP_W_3 15 +#define R600_CLIP__PA_CL_UCP_X_4 16 +#define R600_CLIP__PA_CL_UCP_Y_4 17 +#define R600_CLIP__PA_CL_UCP_Z_4 18 +#define R600_CLIP__PA_CL_UCP_W_4 19 +#define R600_CLIP__PA_CL_UCP_X_5 20 +#define R600_CLIP__PA_CL_UCP_Y_5 21 +#define R600_CLIP__PA_CL_UCP_Z_5 22 +#define R600_CLIP__PA_CL_UCP_W_5 23 +#define R600_CLIP_SIZE 24 +#define R600_CLIP_PM4 128 +/* R600 QUERY BEGIN/END */ +#define R600_QUERY__OFFSET 0 +#define R600_QUERY_SIZE 1 +#define R600_QUERY_PM4 128 #endif |