1 files changed, 178 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c
new file mode 100644
index 00000000000..bdda7e148c6
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_uvd.c
@@ -0,0 +1,178 @@
+/**************************************************************************
+ *
+ * Copyright 2011 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/*
+ * Authors:
+ *      Christian König <[email protected]>
+ *
+ */
+
+#include <sys/types.h>
+#include <assert.h>
+#include <errno.h>
+#include <unistd.h>
+
+#include "pipe/p_video_decoder.h"
+
+#include "util/u_memory.h"
+#include "util/u_video.h"
+
+#include "vl/vl_defines.h"
+#include "vl/vl_mpeg12_decoder.h"
+
+#include "r600_pipe.h"
+#include "radeon/radeon_uvd.h"
+#include "r600d.h"
+
+/**
+ * creates an video buffer with an UVD compatible memory layout
+ */
+struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
+						   const struct pipe_video_buffer *tmpl)
+{
+	struct r600_context *ctx = (struct r600_context *)pipe;
+	struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
+	struct radeon_surface* surfaces[VL_NUM_COMPONENTS] = {};
+	struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
+	const enum pipe_format *resource_formats;
+	struct pipe_video_buffer template;
+	struct pipe_resource templ;
+	unsigned i, depth;
+
+	assert(pipe);
+
+	/* first create the needed resources as "normal" textures */
+	resource_formats = vl_video_buffer_formats(pipe->screen, tmpl->buffer_format);
+	if (!resource_formats)
+		return NULL;
+
+	depth = tmpl->interlaced ? 2 : 1;
+	template = *tmpl;
+	template.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
+	template.height = align(tmpl->height / depth, VL_MACROBLOCK_HEIGHT);
+
+	vl_vide_buffer_template(&templ, &template, resource_formats[0], depth, PIPE_USAGE_STATIC, 0);
+	resources[0] = (struct r600_texture *)
+		pipe->screen->resource_create(pipe->screen, &templ);
+	if (!resources[0])
+		goto error;
+
+	if (resource_formats[1] != PIPE_FORMAT_NONE) {
+		vl_vide_buffer_template(&templ, &template, resource_formats[1], depth, PIPE_USAGE_STATIC, 1);
+		resources[1] = (struct r600_texture *)
+			pipe->screen->resource_create(pipe->screen, &templ);
+		if (!resources[1])
+			goto error;
+	}
+
+	if (resource_formats[2] != PIPE_FORMAT_NONE) {
+		vl_vide_buffer_template(&templ, &template, resource_formats[2], depth, PIPE_USAGE_STATIC, 2);
+		resources[2] = (struct r600_texture *)
+			pipe->screen->resource_create(pipe->screen, &templ);
+		if (!resources[2])
+			goto error;
+	}
+
+	for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
+		if (!resources[i])
+			continue;
+
+		pbs[i] = &resources[i]->resource.buf;
+		surfaces[i] = &resources[i]->surface;
+
+		if (ctx->chip_class < EVERGREEN) {
+			resources[i]->array_mode[0] = V_038000_ARRAY_LINEAR_ALIGNED;
+			resources[i]->surface.level[0].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
+		}
+	}
+
+	ruvd_join_surfaces(ctx->ws, templ.bind, pbs, surfaces);
+
+	for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
+		if (!resources[i])
+			continue;
+
+		/* recreate the CS handle */
+		resources[i]->resource.cs_buf = ctx->ws->buffer_get_cs_handle(
+			resources[i]->resource.buf);
+	}
+
+	template.height *= depth;
+	return vl_video_buffer_create_ex2(pipe, &template, (struct pipe_resource **)resources);
+
+error:
+	for (i = 0; i < VL_NUM_COMPONENTS; ++i)
+		pipe_resource_reference((struct pipe_resource **)&resources[i], NULL);
+
+	return NULL;
+}
+
+/* hw encode the number of memory banks */
+static uint32_t eg_num_banks(uint32_t nbanks)
+{
+	switch (nbanks) {
+	case 2:
+		return 0;
+	case 4:
+		return 1;
+	case 8:
+	default:
+		return 2;
+	case 16:
+		return 3;
+	}
+}
+
+/* set the decoding target buffer offsets */
+static struct radeon_winsys_cs_handle* r600_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
+{
+	struct r600_screen *rscreen = (struct r600_screen*)buf->base.context->screen;
+	struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
+	struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
+
+	msg->decode.dt_field_mode = buf->base.interlaced;
+	msg->decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->tiling_info.num_banks));
+
+	ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
+
+	return luma->resource.cs_buf;
+}
+
+/* create decoder */
+struct pipe_video_decoder *r600_uvd_create_decoder(struct pipe_context *context,
+						   enum pipe_video_profile profile,
+						   enum pipe_video_entrypoint entrypoint,
+						   enum pipe_video_chroma_format chroma_format,
+						   unsigned width, unsigned height,
+						   unsigned max_references, bool expect_chunked_decode)
+{
+	struct r600_context *ctx = (struct r600_context *)context;
+
+	return ruvd_create_decoder(context, profile, entrypoint, chroma_format,
+			 	   width, height, max_references, expect_chunked_decode,
+				   ctx->ws, r600_uvd_set_dtb);
+}