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path: root/src/gallium/drivers/r600/r600_hw_states.c
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Diffstat (limited to 'src/gallium/drivers/r600/r600_hw_states.c')
-rw-r--r--src/gallium/drivers/r600/r600_hw_states.c40
1 files changed, 20 insertions, 20 deletions
diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c
index b7070d7d6eb..1974b20d862 100644
--- a/src/gallium/drivers/r600/r600_hw_states.c
+++ b/src/gallium/drivers/r600/r600_hw_states.c
@@ -120,7 +120,7 @@ static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
rbuffer = &rtex->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
@@ -171,7 +171,7 @@ static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
rtex->depth = 1;
rbuffer = &rtex->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
level = state->zsbuf->level;
@@ -537,11 +537,11 @@ static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
if (r) {
return;
}
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], tmp->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], tmp->uncompressed);
} else {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
}
rstate->nbo = 2;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -873,10 +873,10 @@ static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resou
struct r600_screen *rscreen = rctx->screen;
radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
- vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
vs_resource->nbo = 1;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
- vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) |
S_038008_DATA_FORMAT(format);
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
@@ -899,7 +899,7 @@ static int r600_draw_vgt_init(struct r600_draw *draw,
draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
draw->draw.states[R600_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
if (rbuffer) {
- draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
draw->draw.nbo = 1;
@@ -980,7 +980,7 @@ static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state *
state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
S_028868_STACK_SIZE(rshader->bc.nstack);
state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
- state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
state->nbo = 1;
state->placement[0] = RADEON_GEM_DOMAIN_GTT;
return radeon_state_pm4(state);
@@ -1005,8 +1005,8 @@ static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *
state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
S_028868_STACK_SIZE(rshader->bc.nstack);
- state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
- state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
+ radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
state->nbo = 2;
state->placement[0] = RADEON_GEM_DOMAIN_GTT;
state->placement[2] = RADEON_GEM_DOMAIN_GTT;
@@ -1070,18 +1070,18 @@ static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resou
format = r600_translate_colorformat(rtexture->resource.base.b.format);
swap = r600_translate_colorswap(rtexture->resource.base.b.format);
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
- rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rtexture->uncompressed);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rtexture->uncompressed);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 3;
color_info = 0;
} else {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
@@ -1126,7 +1126,7 @@ static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resou
rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
S_028000_SLICE_TILE_MAX(slice);
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
@@ -1262,7 +1262,7 @@ void r600_set_constant_buffer_mem(struct pipe_context *ctx,
rstate->states[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
rstate->states[R600_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
if (radeon_state_pm4(rstate))
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 15:40:24 +0000