diff options
Diffstat (limited to 'src/gallium/drivers/r600/evergreen_state.c')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 33 |
1 files changed, 6 insertions, 27 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index eec567c7150..5224e420119 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -35,13 +35,12 @@ static inline unsigned evergreen_array_mode(unsigned mode) { switch (mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED; break; case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1; break; case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1; - default: - case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL; } } @@ -758,6 +757,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, non_disp_tiling = tmp->non_disp_tiling; switch (surflevel[base_level].mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: array_mode = V_028C70_ARRAY_LINEAR_ALIGNED; break; @@ -767,10 +767,6 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, case RADEON_SURF_MODE_1D: array_mode = V_028C70_ARRAY_1D_TILED_THIN1; break; - case RADEON_SURF_MODE_LINEAR: - default: - array_mode = V_028C70_ARRAY_LINEAR_GENERAL; - break; } macro_aspect = tmp->surface.mtilea; bankw = tmp->surface.bankw; @@ -1006,14 +1002,8 @@ void evergreen_init_color_surface(struct r600_context *rctx, bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE; offset = rtex->surface.level[level].offset; - if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { - assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); - offset += rtex->surface.level[level].slice_size * - surf->base.u.tex.first_layer; - color_view = 0; - } else - color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | - S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); + color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | + S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; @@ -1022,6 +1012,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, } color_info = 0; switch (rtex->surface.level[level].mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED); non_disp_tiling = 1; @@ -1034,11 +1025,6 @@ void evergreen_init_color_surface(struct r600_context *rctx, color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1); non_disp_tiling = rtex->non_disp_tiling; break; - case RADEON_SURF_MODE_LINEAR: - default: - color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL); - non_disp_tiling = 1; - break; } tile_split = rtex->surface.tile_split; macro_aspect = rtex->surface.mtilea; @@ -1201,7 +1187,6 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, break; case RADEON_SURF_MODE_1D: case RADEON_SURF_MODE_LINEAR_ALIGNED: - case RADEON_SURF_MODE_LINEAR: default: array_mode = V_028C70_ARRAY_1D_TILED_THIN1; break; @@ -3391,9 +3376,6 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; assert(dst_mode != src_mode); /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */ @@ -3406,7 +3388,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, pitch_tile_max = ((pitch / bpp) / 8) - 1; nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks); - if (dst_mode == RADEON_SURF_MODE_LINEAR) { + if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) { /* T2L */ array_mode = evergreen_array_mode(src_mode); slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8); @@ -3538,9 +3520,6 @@ static void evergreen_dma_copy(struct pipe_context *ctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) { /* FIXME evergreen can do partial blit */ |