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-rw-r--r--src/gallium/drivers/r300/r300_surface.c121
1 files changed, 54 insertions, 67 deletions
diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c
index 3672f60b1b8..86fe3fc4f97 100644
--- a/src/gallium/drivers/r300/r300_surface.c
+++ b/src/gallium/drivers/r300/r300_surface.c
@@ -23,6 +23,55 @@
#include "r300_surface.h"
+static void r300_surface_setup(struct pipe_context* pipe,
+ struct pipe_surface* dest,
+ unsigned x, unsigned y,
+ unsigned w, unsigned h)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ CS_LOCALS(r300);
+ struct r300_capabilities* caps = r300_screen(pipe->screen)->caps;
+ struct r300_texture* tex = (struct r300_texture*)dest->texture;
+ unsigned pixpitch = tex->stride / tex->tex.block.size;
+
+ r300_emit_blend_state(r300, &blend_clear_state);
+ r300_emit_blend_color_state(r300, &blend_color_clear_state);
+ r300_emit_dsa_state(r300, &dsa_clear_state);
+ r300_emit_rs_state(r300, &rs_clear_state);
+
+ BEGIN_CS(15);
+
+ /* Pixel scissors. */
+ OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
+ if (caps->is_r500) {
+ OUT_CS((x << R300_SCISSORS_X_SHIFT) | (y << R300_SCISSORS_Y_SHIFT));
+ OUT_CS((w << R300_SCISSORS_X_SHIFT) | (h << R300_SCISSORS_Y_SHIFT));
+ } else {
+ /* Non-R500 chipsets have an offset of 1440 in their scissors. */
+ OUT_CS(((x + 1440) << R300_SCISSORS_X_SHIFT) |
+ ((y + 1440) << R300_SCISSORS_Y_SHIFT));
+ OUT_CS(((w + 1440) << R300_SCISSORS_X_SHIFT) |
+ ((h + 1440) << R300_SCISSORS_Y_SHIFT));
+ }
+
+ /* Flush colorbuffer and blend caches. */
+ OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
+ R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
+ R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
+ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
+
+ /* Setup colorbuffer. */
+ OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
+ OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+ OUT_CS_REG(R300_RB3D_COLORPITCH0, pixpitch |
+ r300_translate_colorformat(tex->tex.format));
+ OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0xf);
+
+ END_CS;
+}
+
/* Provides pipe_context's "surface_fill". Commonly used for clearing
* buffers. */
static void r300_surface_fill(struct pipe_context* pipe,
@@ -53,10 +102,7 @@ static void r300_surface_fill(struct pipe_context* pipe,
return;
}
- r300_emit_blend_state(r300, &blend_clear_state);
- r300_emit_blend_color_state(r300, &blend_color_clear_state);
- r300_emit_dsa_state(r300, &dsa_clear_state);
- r300_emit_rs_state(r300, &rs_clear_state);
+ r300_surface_setup(r300, dest, x, y, w, h);
/* Fragment shader setup */
if (caps->is_r500) {
@@ -67,7 +113,7 @@ static void r300_surface_fill(struct pipe_context* pipe,
r300_emit_rs_block_state(r300, &r300_rs_block_clear_state);
}
- BEGIN_CS(36);
+ BEGIN_CS(21);
/* Viewport setup */
OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
@@ -78,37 +124,11 @@ static void r300_surface_fill(struct pipe_context* pipe,
OUT_CS_32F(1.0);
OUT_CS_32F(0.0);
- /* Pixel scissors */
- OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
- if (caps->is_r500) {
- OUT_CS((x << R300_SCISSORS_X_SHIFT) | (y << R300_SCISSORS_Y_SHIFT));
- OUT_CS((w << R300_SCISSORS_X_SHIFT) | (h << R300_SCISSORS_Y_SHIFT));
- } else {
- /* Non-R500 chipsets have an offset of 1440 in their scissors. */
- OUT_CS(((x + 1440) << R300_SCISSORS_X_SHIFT) |
- ((y + 1440) << R300_SCISSORS_Y_SHIFT));
- OUT_CS(((w + 1440) << R300_SCISSORS_X_SHIFT) |
- ((h + 1440) << R300_SCISSORS_Y_SHIFT));
- }
-
/* The size of the point we're about to draw, in sixths of pixels */
OUT_CS_REG(R300_GA_POINT_SIZE,
((h * 6) & R300_POINTSIZE_Y_MASK) |
((w * 6) << R300_POINTSIZE_X_SHIFT));
- /* Flush colorbuffer and blend caches. */
- OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
- R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
- R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
- OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
- R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
- R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
-
- OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
- OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- OUT_CS_REG(R300_RB3D_COLORPITCH0, pixpitch |
- r300_translate_colorformat(tex->tex.format));
- OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
/* XXX Packet3 */
OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
@@ -151,47 +171,14 @@ static void r300_surface_copy(struct pipe_context* pipe,
" dimensions %dx%d (pixel pitch %d)\n",
src, srcx, srcy, dest, destx, desty, w, h, pixpitch);
+ /* if ((srctex == desttex) &&
+ ((destx < srcx + w) || (srcx < destx + w)) &&
+ ((desty < srcy + h) || (srcy < destx + h))) { */
if (TRUE) {
debug_printf("r300: Falling back on surface_copy\n");
return util_surface_copy(pipe, FALSE, dest, destx, desty, src,
srcx, srcy, w, h);
}
-#if 0
- BEGIN_CS();
- OUT_CS_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT,(RADEON_DEFAULT_SC_RIGHT_MAX |
- RADEON_DEFAULT_SC_BOTTOM_MAX));
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
- RADEON_GMC_BRUSH_NONE |
- (datatype << 8) |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- RADEON_ROP[rop].rop |
- RADEON_DP_SRC_SOURCE_MEMORY |
- RADEON_GMC_CLR_CMP_CNTL_DIS));
- OUT_CS_REG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
- OUT_CS_REG(RADEON_DP_BRUSH_BKGD_CLR, 0x0);
- OUT_CS_REG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
- OUT_CS_REG(RADEON_DP_SRC_BKGD_CLR, 0x0);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_DP_CNTL, ((info->accel_state->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
- (info->accel_state->ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0));
-);
-
- OUT_CS_REG_SEQ(RADEON_DST_PITCH_OFFSET, 1);
- OUT_CS_RELOC(desttex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
-
- OUT_CS_REG_SEQ(RADEON_SRC_PITCH_OFFSET, 1);
- OUT_CS_RELOC(srctex->buffer, 0,
- RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
-
- OUT_CS_REG(RADEON_SRC_Y_X, (srcy << 16) | srcx);
- OUT_CS_REG(RADEON_DST_Y_X, (desty << 16) | destx);
- OUT_CS_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
- OUT_CS_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
- OUT_CS_REG(RADEON_WAIT_UNTIL,
- RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
- END_CS;
-#endif
}
void r300_init_surface_functions(struct r300_context* r300)
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 06:47:45 +0000