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-rw-r--r--src/gallium/drivers/nv50/nv50_program.c23
-rw-r--r--src/gallium/drivers/nv50/nv50_push.c11
-rw-r--r--src/gallium/drivers/nv50/nv50_screen.c30
-rw-r--r--src/gallium/drivers/nv50/nv50_transfer.c4
4 files changed, 55 insertions, 13 deletions
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index 0156ff95ff9..97f938e6980 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -4208,9 +4208,12 @@ static void
nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
{
struct nouveau_channel *chan = nv50->screen->base.channel;
+ struct nouveau_grobj *tesla = nv50->screen->tesla;
struct nv50_program_exec *e;
uint32_t *up, i;
boolean upload = FALSE;
+ unsigned offset;
+ int width;
if (!p->bo) {
nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
@@ -4267,10 +4270,22 @@ nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
NOUVEAU_ERR("0x%08x\n", e->inst[1]);
}
#endif
- nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
- NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
- up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
- 0, 0, p->exec_size * 4, 1, 1);
+
+ /* SIFC_HEIGHT/SIFC_WIDTH of 65536 do not work, and are not reported
+ * as data error either. hw bug ? */
+#define SIFC_MAX_WIDTH (65536 - 256)
+ offset = 0;
+ width = p->exec_size * 4;
+ while (width > 0) {
+ nv50_upload_sifc(nv50, p->bo, offset, NOUVEAU_BO_VRAM,
+ NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
+ &up[offset / 4], NV50_2D_SIFC_FORMAT_R8_UNORM,
+ 0, 0, 0, MIN2(SIFC_MAX_WIDTH, width), 1, 1);
+ width -= SIFC_MAX_WIDTH;
+ offset += SIFC_MAX_WIDTH;
+ }
+ BEGIN_RING(chan, tesla, NV50TCL_CODE_CB_FLUSH, 1);
+ OUT_RING (chan, 0);
FREE(up);
}
diff --git a/src/gallium/drivers/nv50/nv50_push.c b/src/gallium/drivers/nv50/nv50_push.c
index 244242b8434..c3ac8041462 100644
--- a/src/gallium/drivers/nv50/nv50_push.c
+++ b/src/gallium/drivers/nv50/nv50_push.c
@@ -108,7 +108,7 @@ emit_vertex(struct push_context *ctx, unsigned n)
int i;
if (ctx->edgeflag_attr < 16) {
- float *edgeflag = ctx->attr[ctx->edgeflag_attr].map +
+ float *edgeflag = (uint8_t *)ctx->attr[ctx->edgeflag_attr].map +
ctx->attr[ctx->edgeflag_attr].stride * n;
if (*edgeflag != ctx->edgeflag) {
@@ -120,7 +120,8 @@ emit_vertex(struct push_context *ctx, unsigned n)
BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, ctx->vtx_size);
for (i = 0; i < ctx->attr_nr; i++)
- ctx->attr[i].push(chan, ctx->attr[i].map + ctx->attr[i].stride * n);
+ ctx->attr[i].push(chan,
+ (uint8_t *)ctx->attr[i].map + ctx->attr[i].stride * n);
}
static void
@@ -243,14 +244,14 @@ nv50_push_elements_instanced(struct pipe_context *pipe,
assert(bo->map);
return;
}
- ctx.attr[n].map = bo->map + vb->buffer_offset + ve->src_offset;
+ ctx.attr[n].map = (uint8_t *)bo->map + vb->buffer_offset + ve->src_offset;
nouveau_bo_unmap(bo);
ctx.attr[n].stride = vb->stride;
ctx.attr[n].divisor = ve->instance_divisor;
if (ctx.attr[n].divisor) {
ctx.attr[n].step = i_start % ve->instance_divisor;
- ctx.attr[n].map += i_start * vb->stride;
+ ctx.attr[n].map = (uint8_t *)ctx.attr[n].map + i_start * vb->stride;
}
size = util_format_get_component_bits(ve->src_format,
@@ -331,7 +332,7 @@ nv50_push_elements_instanced(struct pipe_context *pipe,
ctx.attr[i].divisor != ++ctx.attr[i].step)
continue;
ctx.attr[i].step = 0;
- ctx.attr[i].map += ctx.attr[i].stride;
+ ctx.attr[i].map = (uint8_t *)ctx.attr[i].map + ctx.attr[i].stride;
}
u_split_prim_init(&s, mode, start, count);
diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c
index ff3a7b2843d..757f13b640a 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -125,6 +125,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 8;
case PIPE_CAP_OCCLUSION_QUERY:
return 1;
+ case PIPE_CAP_TIMER_QUERY:
+ return 0;
case PIPE_CAP_TEXTURE_SHADOW_MAP:
return 1;
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
@@ -150,6 +152,34 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
return 0;
+ case PIPE_CAP_MAX_VS_INSTRUCTIONS:
+ case PIPE_CAP_MAX_FS_INSTRUCTIONS:
+ case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
+ case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
+ case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
+ case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
+ case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
+ case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: /* arbitrary limit */
+ return 16384;
+ case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
+ case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: /* need stack bo */
+ return 4;
+ case PIPE_CAP_MAX_VS_INPUTS:
+ return 16;
+ case PIPE_CAP_MAX_FS_INPUTS: /* 128 / 4 with GP */
+ return 64 / 4;
+ case PIPE_CAP_MAX_VS_CONSTS:
+ case PIPE_CAP_MAX_FS_CONSTS:
+ return 65536 / 16;
+ case PIPE_CAP_MAX_VS_ADDRS:
+ case PIPE_CAP_MAX_FS_ADDRS: /* no spilling atm */
+ return 1;
+ case PIPE_CAP_MAX_VS_PREDS:
+ case PIPE_CAP_MAX_FS_PREDS: /* not yet handled */
+ return 0;
+ case PIPE_CAP_MAX_VS_TEMPS:
+ case PIPE_CAP_MAX_FS_TEMPS: /* no spilling atm */
+ return 128 / 4;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0;
diff --git a/src/gallium/drivers/nv50/nv50_transfer.c b/src/gallium/drivers/nv50/nv50_transfer.c
index c5581a6f9d0..f973cf24b98 100644
--- a/src/gallium/drivers/nv50/nv50_transfer.c
+++ b/src/gallium/drivers/nv50/nv50_transfer.c
@@ -274,7 +274,6 @@ nv50_upload_sifc(struct nv50_context *nv50,
{
struct nouveau_channel *chan = nv50->screen->base.channel;
struct nouveau_grobj *eng2d = nv50->screen->eng2d;
- struct nouveau_grobj *tesla = nv50->screen->tesla;
unsigned line_dwords = (w * cpp + 3) / 4;
reloc |= NOUVEAU_BO_WR;
@@ -346,7 +345,4 @@ nv50_upload_sifc(struct nv50_context *nv50,
src = (uint8_t *) src + src_pitch;
}
-
- BEGIN_RING(chan, tesla, NV50TCL_CODE_CB_FLUSH, 1);
- OUT_RING (chan, 0);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 06:46:58 +0000