diff options
Diffstat (limited to 'src/gallium/drivers/nouveau')
104 files changed, 1538 insertions, 1086 deletions
diff --git a/src/gallium/drivers/nouveau/Makefile.am b/src/gallium/drivers/nouveau/Makefile.am index d05f0a17ab4..c52d62e54a2 100644 --- a/src/gallium/drivers/nouveau/Makefile.am +++ b/src/gallium/drivers/nouveau/Makefile.am @@ -20,8 +20,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER # DEALINGS IN THE SOFTWARE. -AUTOMAKE_OPTIONS = subdir-objects - include Makefile.sources include $(top_srcdir)/src/gallium/Automake.inc diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp index ca3c806e92f..cce60550ae5 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp @@ -1153,8 +1153,8 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info) switch (info->type) { PROG_TYPE_CASE(VERTEX, VERTEX); -// PROG_TYPE_CASE(HULL, TESSELLATION_CONTROL); -// PROG_TYPE_CASE(DOMAIN, TESSELLATION_EVAL); + PROG_TYPE_CASE(TESS_CTRL, TESSELLATION_CONTROL); + PROG_TYPE_CASE(TESS_EVAL, TESSELLATION_EVAL); PROG_TYPE_CASE(GEOMETRY, GEOMETRY); PROG_TYPE_CASE(FRAGMENT, FRAGMENT); PROG_TYPE_CASE(COMPUTE, COMPUTE); diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h b/src/gallium/drivers/nouveau/codegen/nv50_ir.h index 529dcb9bdc2..3ddaeafebbd 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h @@ -106,6 +106,7 @@ enum operation OP_MEMBAR, // memory barrier (mfence, lfence, sfence) OP_VFETCH, // indirection 0 in attribute space, indirection 1 is vertex base OP_PFETCH, // fetch base address of vertex src0 (immediate) [+ src1] + OP_AFETCH, // fetch base address of shader input (a[%r1+0x10]) OP_EXPORT, OP_LINTERP, OP_PINTERP, @@ -372,7 +373,8 @@ enum SVSemantic SV_SAMPLE_INDEX, SV_SAMPLE_POS, SV_SAMPLE_MASK, - SV_TESS_FACTOR, + SV_TESS_OUTER, + SV_TESS_INNER, SV_TESS_COORD, SV_TID, SV_CTAID, diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp index 51b9225156b..fa8ee072a92 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp @@ -332,6 +332,9 @@ BasicBlock::splitBefore(Instruction *insn, bool attach) BasicBlock *bb = new BasicBlock(func); assert(!insn || insn->op != OP_PHI); + bb->joinAt = joinAt; + joinAt = NULL; + splitCommon(insn, bb, attach); return bb; } diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp index 708c5b322ee..19418c0e0f1 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp @@ -428,8 +428,7 @@ BuildUtil::mkSysVal(SVSemantic svName, uint32_t svIndex) { Symbol *sym = new_Symbol(prog, FILE_SYSTEM_VALUE, 0); - assert(svIndex < 4 || - (svName == SV_CLIP_DISTANCE || svName == SV_TESS_FACTOR)); + assert(svIndex < 4 || svName == SV_CLIP_DISTANCE); switch (svName) { case SV_POSITION: @@ -438,7 +437,9 @@ BuildUtil::mkSysVal(SVSemantic svName, uint32_t svIndex) case SV_POINT_SIZE: case SV_POINT_COORD: case SV_CLIP_DISTANCE: - case SV_TESS_FACTOR: + case SV_TESS_OUTER: + case SV_TESS_INNER: + case SV_TESS_COORD: sym->reg.type = TYPE_F32; break; default: diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h index dba56bf2716..2b9edcf9172 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h @@ -69,18 +69,6 @@ struct nv50_ir_varying # define NV50_IR_DEBUG_REG_ALLOC 0 #endif -#define NV50_SEMANTIC_CLIPDISTANCE (TGSI_SEMANTIC_COUNT + 0) -#define NV50_SEMANTIC_TESSFACTOR (TGSI_SEMANTIC_COUNT + 7) -#define NV50_SEMANTIC_TESSCOORD (TGSI_SEMANTIC_COUNT + 8) -#define NV50_SEMANTIC_COUNT (TGSI_SEMANTIC_COUNT + 10) - -#define NV50_TESS_PART_FRACT_ODD 0 -#define NV50_TESS_PART_FRACT_EVEN 1 -#define NV50_TESS_PART_POW2 2 -#define NV50_TESS_PART_INTEGER 3 - -#define NV50_PRIM_PATCHES PIPE_PRIM_MAX - struct nv50_ir_prog_symbol { uint32_t label; @@ -151,10 +139,10 @@ struct nv50_ir_prog_info } gp; struct { unsigned numColourResults; - boolean writesDepth; - boolean earlyFragTests; - boolean separateFragData; - boolean usesDiscard; + bool writesDepth; + bool earlyFragTests; + bool separateFragData; + bool usesDiscard; } fp; struct { uint32_t inputOffset; /* base address for user args */ @@ -180,11 +168,11 @@ struct nv50_ir_prog_info int8_t viewportId; /* output index of ViewportIndex */ uint8_t fragDepth; /* output index of FragDepth */ uint8_t sampleMask; /* output index of SampleMask */ - boolean sampleInterp; /* perform sample interp on all fp inputs */ + bool sampleInterp; /* perform sample interp on all fp inputs */ uint8_t backFaceColor[2]; /* input/output indices of back face colour */ uint8_t globalAccess; /* 1 for read, 2 for wr, 3 for rw */ - boolean fp64; /* program uses fp64 math */ - boolean nv50styleSurfaces; /* generate gX[] access for raw buffers */ + bool fp64; /* program uses fp64 math */ + bool nv50styleSurfaces; /* generate gX[] access for raw buffers */ uint8_t resInfoCBSlot; /* cX[] used for tex handles, surface info */ uint16_t texBindBase; /* base address for tex handles (nve4) */ uint16_t suInfoBase; /* base address for surface info (nve4) */ diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index ab8bf2e5504..f06056f8f17 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp @@ -77,6 +77,7 @@ private: void emitMOV(const Instruction *); void emitINTERP(const Instruction *); + void emitAFETCH(const Instruction *); void emitPFETCH(const Instruction *); void emitVFETCH(const Instruction *); void emitEXPORT(const Instruction *); @@ -120,6 +121,8 @@ private: void emitPIXLD(const Instruction *); + void emitBAR(const Instruction *); + void emitFlow(const Instruction *); inline void defId(const ValueDef&, const int pos); @@ -1250,6 +1253,13 @@ CodeEmitterGK110::emitPIXLD(const Instruction *i) } void +CodeEmitterGK110::emitBAR(const Instruction *i) +{ + /* TODO */ + emitNOP(i); +} + +void CodeEmitterGK110::emitFlow(const Instruction *i) { const FlowInstruction *f = i->asFlow(); @@ -1330,6 +1340,23 @@ CodeEmitterGK110::emitFlow(const Instruction *i) } void +CodeEmitterGK110::emitAFETCH(const Instruction *i) +{ + uint32_t offset = i->src(0).get()->reg.data.offset & 0x7ff; + + code[0] = 0x00000002 | (offset << 23); + code[1] = 0x7d000000 | (offset >> 9); + + if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT) + code[1] |= 0x8; + + emitPredicate(i); + + defId(i->def(0), 2); + srcId(i->src(0).getIndirect(0), 10); +} + +void CodeEmitterGK110::emitPFETCH(const Instruction *i) { uint32_t prim = i->src(0).get()->reg.data.u32; @@ -1698,6 +1725,9 @@ CodeEmitterGK110::emitInstruction(Instruction *insn) case OP_EXPORT: emitEXPORT(insn); break; + case OP_AFETCH: + emitAFETCH(insn); + break; case OP_PFETCH: emitPFETCH(insn); break; @@ -1856,6 +1886,9 @@ CodeEmitterGK110::emitInstruction(Instruction *insn) emitNOP(insn); insn->join = 1; break; + case OP_BAR: + emitBAR(insn); + break; case OP_PHI: case OP_UNION: case OP_CONSTRAINT: diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp index 399a6f1db13..ef5c87d0437 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp @@ -174,6 +174,7 @@ private: void emitALD(); void emitAST(); void emitISBERD(); + void emitAL2P(); void emitIPA(); void emitPIXLD(); @@ -2204,6 +2205,17 @@ CodeEmitterGM107::emitISBERD() } void +CodeEmitterGM107::emitAL2P() +{ + emitInsn (0xefa00000); + emitField(0x2f, 2, (insn->getDef(0)->reg.size / 4) - 1); + emitO (0x20); + emitField(0x14, 11, insn->src(0).get()->reg.data.offset); + emitGPR (0x08, insn->src(0).getIndirect(0)); + emitGPR (0x00, insn->def(0)); +} + +void CodeEmitterGM107::emitIPA() { int ipam = 0, ipas = 0; @@ -2441,8 +2453,14 @@ CodeEmitterGM107::emitTXQ() break; } - emitInsn (0xdf4a0000); - emitField(0x24, 13, insn->tex.r); + if (insn->tex.rIndirectSrc >= 0) { + emitInsn (0xdf500000); + } else { + emitInsn (0xdf480000); + emitField(0x24, 13, insn->tex.r); + } + + emitField(0x31, 1, insn->tex.liveOnly); emitField(0x1f, 4, insn->tex.mask); emitField(0x16, 6, type); emitGPR (0x08, insn->src(0)); @@ -2753,6 +2771,9 @@ CodeEmitterGM107::emitInstruction(Instruction *i) case OP_PFETCH: emitISBERD(); break; + case OP_AFETCH: + emitAL2P(); + break; case OP_LINTERP: case OP_PINTERP: emitIPA(); diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp index 1bfc8e32e84..67ea6df773c 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp @@ -499,10 +499,14 @@ CodeEmitterNV50::emitForm_MAD(const Instruction *i) setSrc(i, 2, 2); if (i->getIndirect(0, 0)) { - assert(!i->getIndirect(1, 0)); + assert(!i->srcExists(1) || !i->getIndirect(1, 0)); + assert(!i->srcExists(2) || !i->getIndirect(2, 0)); setAReg16(i, 0); - } else { + } else if (i->srcExists(1) && i->getIndirect(1, 0)) { + assert(!i->srcExists(2) || !i->getIndirect(2, 0)); setAReg16(i, 1); + } else { + setAReg16(i, 2); } } @@ -546,7 +550,7 @@ CodeEmitterNV50::emitForm_MUL(const Instruction *i) } // usual immediate form -// - 1 to 3 sources where last is immediate (rir, gir) +// - 1 to 3 sources where second is immediate (rir, gir) // - no address or predicate possible void CodeEmitterNV50::emitForm_IMM(const Instruction *i) @@ -562,7 +566,7 @@ CodeEmitterNV50::emitForm_IMM(const Instruction *i) if (Target::operationSrcNr[i->op] > 1) { setSrc(i, 0, 0); setImmediate(i, 1); - setSrc(i, 2, 1); + // If there is another source, it has to be the same as the dest reg. } else { setImmediate(i, 0); } diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index 472e3a84119..f607f3ba3ec 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp @@ -85,6 +85,7 @@ private: void emitCCTL(const Instruction *); void emitINTERP(const Instruction *); + void emitAFETCH(const Instruction *); void emitPFETCH(const Instruction *); void emitVFETCH(const Instruction *); void emitEXPORT(const Instruction *); @@ -1450,6 +1451,7 @@ CodeEmitterNVC0::emitBAR(const Instruction *i) ImmediateValue *imm = i->getSrc(0)->asImm(); assert(imm); code[0] |= imm->reg.data.u32 << 20; + code[1] |= 0x8000; } // thread count @@ -1460,6 +1462,7 @@ CodeEmitterNVC0::emitBAR(const Instruction *i) assert(imm); code[0] |= imm->reg.data.u32 << 26; code[1] |= imm->reg.data.u32 >> 6; + code[1] |= 0x4000; } if (i->srcExists(2) && (i->predSrc != 2)) { @@ -1494,6 +1497,21 @@ CodeEmitterNVC0::emitBAR(const Instruction *i) } void +CodeEmitterNVC0::emitAFETCH(const Instruction *i) +{ + code[0] = 0x00000006; + code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff); + + if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT) + code[0] |= 0x200; + + emitPredicate(i); + + defId(i->def(0), 14); + srcId(i->src(0).getIndirect(0), 20); +} + +void CodeEmitterNVC0::emitPFETCH(const Instruction *i) { uint32_t prim = i->src(0).get()->reg.data.u32; diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index ecd115f9807..4847a0f3355 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -372,6 +372,10 @@ static nv50_ir::SVSemantic translateSysVal(uint sysval) case TGSI_SEMANTIC_SAMPLEPOS: return nv50_ir::SV_SAMPLE_POS; case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK; case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID; + case TGSI_SEMANTIC_TESSCOORD: return nv50_ir::SV_TESS_COORD; + case TGSI_SEMANTIC_TESSOUTER: return nv50_ir::SV_TESS_OUTER; + case TGSI_SEMANTIC_TESSINNER: return nv50_ir::SV_TESS_INNER; + case TGSI_SEMANTIC_VERTICESIN: return nv50_ir::SV_VERTEX_COUNT; default: assert(0); return nv50_ir::SV_CLOCK; @@ -434,7 +438,6 @@ nv50_ir::DataType Instruction::inferSrcType() const case TGSI_OPCODE_USLT: case TGSI_OPCODE_USNE: case TGSI_OPCODE_USHR: - case TGSI_OPCODE_UCMP: case TGSI_OPCODE_ATOMUADD: case TGSI_OPCODE_ATOMXCHG: case TGSI_OPCODE_ATOMCAS: @@ -827,7 +830,7 @@ Source::Source(struct nv50_ir_prog_info *prog) : info(prog) if (prog->dbgFlags & NV50_IR_DEBUG_BASIC) tgsi_dump(tokens, 0); - mainTempsInLMem = FALSE; + mainTempsInLMem = false; } Source::~Source() @@ -938,7 +941,7 @@ void Source::scanProperty(const struct tgsi_full_property *prop) info->prop.gp.instanceCount = prop->u[0].Data; break; case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS: - info->prop.fp.separateFragData = TRUE; + info->prop.fp.separateFragData = true; break; case TGSI_PROPERTY_FS_COORD_ORIGIN: case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER: @@ -947,6 +950,24 @@ void Source::scanProperty(const struct tgsi_full_property *prop) case TGSI_PROPERTY_VS_PROHIBIT_UCPS: info->io.genUserClip = -1; break; + case TGSI_PROPERTY_TCS_VERTICES_OUT: + info->prop.tp.outputPatchSize = prop->u[0].Data; + break; + case TGSI_PROPERTY_TES_PRIM_MODE: + info->prop.tp.domain = prop->u[0].Data; + break; + case TGSI_PROPERTY_TES_SPACING: + info->prop.tp.partitioning = prop->u[0].Data; + break; + case TGSI_PROPERTY_TES_VERTEX_ORDER_CW: + info->prop.tp.winding = prop->u[0].Data; + break; + case TGSI_PROPERTY_TES_POINT_MODE: + if (prop->u[0].Data) + info->prop.tp.outputPrim = PIPE_PRIM_POINTS; + else + info->prop.tp.outputPrim = PIPE_PRIM_TRIANGLES; /* anything but points */ + break; default: INFO("unhandled TGSI property %d\n", prop->Property.PropertyName); break; @@ -1035,6 +1056,11 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl) if (decl->Interp.Location || info->io.sampleInterp) info->in[i].centroid = 1; } + + if (sn == TGSI_SEMANTIC_PATCH) + info->in[i].patch = 1; + if (sn == TGSI_SEMANTIC_PATCH) + info->numPatchConstants = MAX2(info->numPatchConstants, si + 1); } } break; @@ -1069,6 +1095,13 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl) case TGSI_SEMANTIC_VIEWPORT_INDEX: info->io.viewportId = i; break; + case TGSI_SEMANTIC_PATCH: + info->numPatchConstants = MAX2(info->numPatchConstants, si + 1); + /* fallthrough */ + case TGSI_SEMANTIC_TESSOUTER: + case TGSI_SEMANTIC_TESSINNER: + info->out[i].patch = 1; + break; default: break; } @@ -1092,6 +1125,13 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl) info->sv[i].sn = sn; info->sv[i].si = si; info->sv[i].input = inferSysValDirection(sn); + + switch (sn) { + case TGSI_SEMANTIC_TESSOUTER: + case TGSI_SEMANTIC_TESSINNER: + info->sv[i].patch = 1; + break; + } } break; case TGSI_FILE_RESOURCE: @@ -1156,7 +1196,7 @@ bool Source::scanInstruction(const struct tgsi_full_instruction *inst) } else if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) { if (insn.getDst(0).isIndirect(0)) - mainTempsInLMem = TRUE; + mainTempsInLMem = true; } } @@ -1164,12 +1204,22 @@ bool Source::scanInstruction(const struct tgsi_full_instruction *inst) Instruction::SrcRegister src = insn.getSrc(s); if (src.getFile() == TGSI_FILE_TEMPORARY) { if (src.isIndirect(0)) - mainTempsInLMem = TRUE; + mainTempsInLMem = true; } else if (src.getFile() == TGSI_FILE_RESOURCE) { if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL) info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ? 0x1 : 0x2; + } else + if (src.getFile() == TGSI_FILE_OUTPUT) { + if (src.isIndirect(0)) { + // We don't know which one is accessed, just mark everything for + // reading. This is an extremely unlikely occurrence. + for (unsigned i = 0; i < info->numOutputs; ++i) + info->out[i].oread = 1; + } else { + info->out[src.getIndex(0)].oread = 1; + } } if (src.getFile() != TGSI_FILE_INPUT) continue; @@ -1246,6 +1296,7 @@ private: Value *shiftAddress(Value *); Value *getVertexBase(int s); + Value *getOutputBase(int s); DataArray *getArrayForFile(unsigned file, int idx); Value *fetchSrc(int s, int c); Value *acquireDst(int d, int c); @@ -1343,6 +1394,8 @@ private: Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP) uint8_t vtxBaseValid; + Value *outBase; // base address of vertex out patch (for TCP) + Stack condBBs; // fork BB, then else clause BB Stack joinBBs; // fork BB, for inserting join ops on ENDIF Stack loopBBs; // loop headers @@ -1476,6 +1529,22 @@ Converter::getVertexBase(int s) } Value * +Converter::getOutputBase(int s) +{ + assert(s < 5); + if (!(vtxBaseValid & (1 << s))) { + Value *offset = loadImm(NULL, tgsi.getSrc(s).getIndex(1)); + if (tgsi.getSrc(s).isIndirect(1)) + offset = mkOp2v(OP_ADD, TYPE_U32, getSSA(), + fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL), + offset); + vtxBaseValid |= 1 << s; + vtxBase[s] = mkOp2v(OP_ADD, TYPE_U32, getSSA(), outBase, offset); + } + return vtxBase[s]; +} + +Value * Converter::fetchSrc(int s, int c) { Value *res; @@ -1488,6 +1557,9 @@ Converter::fetchSrc(int s, int c) if (src.is2D()) { switch (src.getFile()) { + case TGSI_FILE_OUTPUT: + dimRel = getOutputBase(s); + break; case TGSI_FILE_INPUT: dimRel = getVertexBase(s); break; @@ -1542,6 +1614,7 @@ Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr) const int idx2d = src.is2D() ? src.getIndex(1) : 0; const int idx = src.getIndex(0); const int swz = src.getSwizzle(c); + Instruction *ld; switch (src.getFile()) { case TGSI_FILE_IMMEDIATE: @@ -1569,13 +1642,19 @@ Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr) if (ptr) return mkLoadv(TYPE_U32, srcToSym(src, c), ptr); } - return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr)); + ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr)); + ld->perPatch = info->in[idx].patch; + return ld->getDef(0); case TGSI_FILE_OUTPUT: - assert(!"load from output file"); - return NULL; + assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL); + ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr)); + ld->perPatch = info->out[idx].patch; + return ld->getDef(0); case TGSI_FILE_SYSTEM_VALUE: assert(!ptr); - return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c)); + ld = mkOp1(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c)); + ld->perPatch = info->sv[idx].patch; + return ld->getDef(0); default: return getArrayForFile(src.getFile(), idx2d)->load( sub.cur->values, idx, swz, shiftAddress(ptr)); @@ -1645,7 +1724,8 @@ Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c, viewport != NULL) mkOp1(OP_MOV, TYPE_U32, viewport, val); else - mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val); + mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val)->perPatch = + info->out[idx].patch; } } else if (f == TGSI_FILE_TEMPORARY || @@ -1687,6 +1767,7 @@ Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork) join->fixed = 1; conv->insertHead(join); + assert(!fork->joinAt); fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv); fork->insertBefore(fork->getExit(), fork->joinAt); } @@ -1728,7 +1809,7 @@ Converter::handleTXQ(Value *dst0[4], enum TexQuery query) } tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level - setTexRS(tex, c, 1, -1); + setTexRS(tex, ++c, 1, -1); bb->insertTail(tex); } @@ -2569,6 +2650,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) } break; case TGSI_OPCODE_UCMP: + srcTy = TYPE_U32; + /* fallthrough */ case TGSI_OPCODE_CMP: FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) { src0 = fetchSrc(0, c); @@ -3282,10 +3365,21 @@ Converter::run() clipVtx[c] = getScratch(); } - if (prog->getType() == Program::TYPE_FRAGMENT) { + switch (prog->getType()) { + case Program::TYPE_TESSELLATION_CONTROL: + outBase = mkOp2v( + OP_SUB, TYPE_U32, getSSA(), + mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)), + mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0))); + break; + case Program::TYPE_FRAGMENT: { Symbol *sv = mkSysVal(SV_POSITION, 3); fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv); mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]); + break; + } + default: + break; } if (info->io.viewportId >= 0) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp index 596ac95d489..1f3fce2bb9a 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp @@ -176,7 +176,7 @@ GM107LoweringPass::handlePOPCNT(Instruction *i) i->getSrc(0), i->getSrc(1)); i->setSrc(0, tmp); i->setSrc(1, NULL); - return TRUE; + return true; } // diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp index 2c7f7e326b2..bea293bac99 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp @@ -871,6 +871,7 @@ NV50LoweringPreSSA::handleTXL(TexInstruction *i) BasicBlock *joinBB = i->bb->splitAfter(i); bld.setPosition(currBB, true); + assert(!currBB->joinAt); currBB->joinAt = bld.mkFlow(OP_JOINAT, joinBB, CC_ALWAYS, NULL); for (int l = 0; l <= 3; ++l) { diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 7a5d1ce0299..c3c302da5c8 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -559,6 +559,12 @@ NVC0LegalizePostRA::visit(BasicBlock *bb) } else if (i->isNop()) { bb->remove(i); + } else + if (i->op == OP_BAR && i->subOp == NV50_IR_SUBOP_BAR_SYNC && + prog->getType() != Program::TYPE_COMPUTE) { + // It seems like barriers are never required for tessellation since + // the warp size is 32, and there are always at most 32 tcs threads. + bb->remove(i); } else { // TODO: Move this to before register allocation for operations that // need the $c register ! @@ -956,7 +962,43 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd) bool NVC0LoweringPass::handleTXQ(TexInstruction *txq) { - // TODO: indirect resource/sampler index + if (txq->tex.rIndirectSrc < 0) + return true; + + Value *ticRel = txq->getIndirectR(); + const int chipset = prog->getTarget()->getChipset(); + + txq->setIndirectS(NULL); + txq->tex.sIndirectSrc = -1; + + assert(ticRel); + + if (chipset < NVISA_GK104_CHIPSET) { + LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa + + txq->setSrc(txq->tex.rIndirectSrc, NULL); + if (txq->tex.r) + ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(), + ticRel, bld.mkImm(txq->tex.r)); + + bld.mkOp2(OP_SHL, TYPE_U32, src, ticRel, bld.mkImm(0x17)); + + txq->moveSources(0, 1); + txq->setSrc(0, src); + } else { + Value *hnd = loadTexHandle( + bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(), + txq->getIndirectR(), bld.mkImm(2)), + txq->tex.r); + txq->tex.r = 0xff; + txq->tex.s = 0x1f; + + txq->setIndirectR(NULL); + txq->moveSources(0, 1); + txq->setSrc(0, hnd); + txq->tex.rIndirectSrc = 0; + } + return true; } @@ -1485,6 +1527,10 @@ NVC0LoweringPass::handleRDSV(Instruction *i) i->op = OP_MOV; i->setSrc(0, bld.mkImm((sv == SV_NTID || sv == SV_NCTAID) ? 1 : 0)); } + if (sv == SV_VERTEX_COUNT) { + bld.setPosition(i, true); + bld.mkOp2(OP_EXTBF, TYPE_U32, i->getDef(0), i->getDef(0), bld.mkImm(0x808)); + } return true; } @@ -1554,7 +1600,7 @@ NVC0LoweringPass::handleRDSV(Instruction *i) ld->subOp = NV50_IR_SUBOP_PIXLD_COVMASK; break; default: - if (prog->getType() == Program::TYPE_TESSELLATION_EVAL) + if (prog->getType() == Program::TYPE_TESSELLATION_EVAL && !i->perPatch) vtx = bld.mkOp1v(OP_PFETCH, TYPE_U32, bld.getSSA(), bld.mkImm(0)); ld = bld.mkFetch(i->getDef(0), i->dType, FILE_SHADER_INPUT, addr, i->getIndirect(0, 0), vtx); @@ -1705,6 +1751,7 @@ NVC0LoweringPass::checkPredicate(Instruction *insn) bool NVC0LoweringPass::visit(Instruction *i) { + bool ret = true; bld.setPosition(i, false); if (i->cc != CC_ALWAYS) @@ -1736,7 +1783,8 @@ NVC0LoweringPass::visit(Instruction *i) case OP_SQRT: return handleSQRT(i); case OP_EXPORT: - return handleEXPORT(i); + ret = handleEXPORT(i); + break; case OP_EMIT: case OP_RESTART: return handleOUT(i); @@ -1775,6 +1823,9 @@ NVC0LoweringPass::visit(Instruction *i) i->setIndirect(0, 0, ptr); i->subOp = NV50_IR_SUBOP_LDC_IS; } + } else if (i->src(0).getFile() == FILE_SHADER_OUTPUT) { + assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL); + i->op = OP_VFETCH; } break; case OP_ATOM: @@ -1796,7 +1847,20 @@ NVC0LoweringPass::visit(Instruction *i) default: break; } - return true; + + /* Kepler+ has a special opcode to compute a new base address to be used + * for indirect loads. + */ + if (targ->getChipset() >= NVISA_GK104_CHIPSET && !i->perPatch && + (i->op == OP_VFETCH || i->op == OP_EXPORT) && i->src(0).isIndirect(0)) { + Instruction *afetch = bld.mkOp1(OP_AFETCH, TYPE_U32, bld.getSSA(), + cloneShallow(func, i->getSrc(0))); + afetch->setIndirect(0, 0, i->getIndirect(0, 0)); + i->src(0).get()->reg.data.offset = 0; + i->setIndirect(0, 0, afetch->getDef(0)); + } + + return ret; } bool diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index ae739eeda83..cea96dcdfc5 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp @@ -608,9 +608,12 @@ ConstantFolding::expr(Instruction *i, case OP_FMA: { i->op = OP_ADD; + /* Move the immediate to the second arg, otherwise the ADD operation + * won't be emittable + */ i->setSrc(1, i->getSrc(0)); - i->src(1).mod = i->src(2).mod; i->setSrc(0, i->getSrc(2)); + i->src(0).mod = i->src(2).mod; i->setSrc(2, NULL); ImmediateValue src0; @@ -2082,6 +2085,8 @@ MemoryOpt::runOpt(BasicBlock *bb) } if (ldst->getPredicate()) // TODO: handle predicated ld/st continue; + if (ldst->perPatch) // TODO: create separate per-patch lists + continue; if (isLoad) { DataFile file = ldst->src(0).getFile(); @@ -2515,6 +2520,8 @@ Instruction::isResultEqual(const Instruction *that) const case FILE_MEMORY_CONST: case FILE_SHADER_INPUT: return true; + case FILE_SHADER_OUTPUT: + return bb->getProgram()->getType() == Program::TYPE_TESSELLATION_EVAL; default: return false; } diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp index ef3de6ff92a..9ebdc6586db 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp @@ -135,6 +135,7 @@ const char *operationStr[OP_LAST + 1] = "membar", "vfetch", "pfetch", + "afetch", "export", "linterp", "pinterp", @@ -258,7 +259,8 @@ static const char *SemanticStr[SV_LAST + 1] = "SAMPLE_INDEX", "SAMPLE_POS", "SAMPLE_MASK", - "TESS_FACTOR", + "TESS_OUTER", + "TESS_INNER", "TESS_COORD", "TID", "CTAID", diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index 898653c9953..78bc97f4397 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -2066,6 +2066,8 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb) condenseDefs(i); if (i->src(0).isIndirect(0) && typeSizeof(i->dType) >= 8) addHazard(i, i->src(0).getIndirect(0)); + if (i->src(0).isIndirect(1) && typeSizeof(i->dType) >= 8) + addHazard(i, i->src(0).getIndirect(1)); } else if (i->op == OP_UNION || i->op == OP_MERGE || diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp index 7992f539782..fe530c76b62 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp @@ -41,7 +41,7 @@ const uint8_t Target::operationSrcNr[] = 0, 0, 0, 0, 0, // BRA, CALL, RET, CONT, BREAK, 0, 0, 0, // PRERET,CONT,BREAK 0, 0, 0, 0, 0, 0, // BRKPT, JOINAT, JOIN, DISCARD, EXIT, MEMBAR - 1, 1, 2, 1, 2, // VFETCH, PFETCH, EXPORT, LINTERP, PINTERP + 1, 1, 1, 2, 1, 2, // VFETCH, PFETCH, AFETCH, EXPORT, LINTERP, PINTERP 1, 1, // EMIT, RESTART 1, 1, 1, // TEX, TXB, TXL, 1, 1, 1, 1, 1, 1, 2, // TXF, TXQ, TXD, TXG, TXLQ, TEXCSAA, TEXPREP @@ -96,8 +96,8 @@ const OpClass Target::operationClass[] = OPCLASS_FLOW, OPCLASS_FLOW, // MEMBAR OPCLASS_CONTROL, - // VFETCH, PFETCH, EXPORT - OPCLASS_LOAD, OPCLASS_OTHER, OPCLASS_STORE, + // VFETCH, PFETCH, AFETCH, EXPORT + OPCLASS_LOAD, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_STORE, // LINTERP, PINTERP OPCLASS_SFU, OPCLASS_SFU, // EMIT, RESTART diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp index ca545a6024a..f3ddcaa5199 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp @@ -118,7 +118,7 @@ void TargetNV50::initOpInfo() static const uint32_t shortForm[(OP_LAST + 31) / 32] = { // MOV,ADD,SUB,MUL,MAD,SAD,L/PINTERP,RCP,TEX,TXF - 0x00014e40, 0x00000040, 0x00000498, 0x00000000 + 0x00014e40, 0x00000040, 0x00000930, 0x00000000 }; static const operation noDestList[] = { diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp index 7d4a859dde4..27df0eba66b 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp @@ -286,7 +286,8 @@ TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const case SV_CLIP_DISTANCE: return 0x2c0 + idx * 4; case SV_POINT_COORD: return 0x2e0 + idx * 4; case SV_FACE: return 0x3fc; - case SV_TESS_FACTOR: return 0x000 + idx * 4; + case SV_TESS_OUTER: return 0x000 + idx * 4; + case SV_TESS_INNER: return 0x010 + idx * 4; case SV_TESS_COORD: return 0x2f0 + idx * 4; case SV_NTID: return kepler ? (0x00 + idx * 4) : ~0; case SV_NCTAID: return kepler ? (0x0c + idx * 4) : ~0; diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c b/src/gallium/drivers/nouveau/nouveau_buffer.c index 09cdbb53ecb..67e181e803a 100644 --- a/src/gallium/drivers/nouveau/nouveau_buffer.c +++ b/src/gallium/drivers/nouveau/nouveau_buffer.c @@ -22,13 +22,13 @@ struct nouveau_transfer { uint32_t offset; }; -static INLINE struct nouveau_transfer * +static inline struct nouveau_transfer * nouveau_transfer(struct pipe_transfer *transfer) { return (struct nouveau_transfer *)transfer; } -static INLINE boolean +static inline bool nouveau_buffer_malloc(struct nv04_resource *buf) { if (!buf->data) @@ -36,16 +36,11 @@ nouveau_buffer_malloc(struct nv04_resource *buf) return !!buf->data; } -static INLINE boolean +static inline bool nouveau_buffer_allocate(struct nouveau_screen *screen, struct nv04_resource *buf, unsigned domain) { - uint32_t size = buf->base.width0; - - if (buf->base.bind & (PIPE_BIND_CONSTANT_BUFFER | - PIPE_BIND_COMPUTE_RESOURCE | - PIPE_BIND_SHADER_RESOURCE)) - size = align(size, 0x100); + uint32_t size = align(buf->base.width0, 0x100); if (domain == NOUVEAU_BO_VRAM) { buf->mm = nouveau_mm_allocate(screen->mm_VRAM, size, @@ -58,12 +53,12 @@ nouveau_buffer_allocate(struct nouveau_screen *screen, buf->mm = nouveau_mm_allocate(screen->mm_GART, size, &buf->bo, &buf->offset); if (!buf->bo) - return FALSE; + return false; NOUVEAU_DRV_STAT(screen, buf_obj_current_bytes_sys, buf->base.width0); } else { assert(domain == 0); if (!nouveau_buffer_malloc(buf)) - return FALSE; + return false; } buf->domain = domain; if (buf->bo) @@ -71,10 +66,10 @@ nouveau_buffer_allocate(struct nouveau_screen *screen, util_range_set_empty(&buf->valid_buffer_range); - return TRUE; + return true; } -static INLINE void +static inline void release_allocation(struct nouveau_mm_allocation **mm, struct nouveau_fence *fence) { @@ -82,7 +77,7 @@ release_allocation(struct nouveau_mm_allocation **mm, (*mm) = NULL; } -INLINE void +inline void nouveau_buffer_release_gpu_storage(struct nv04_resource *buf) { nouveau_bo_ref(NULL, &buf->bo); @@ -98,7 +93,7 @@ nouveau_buffer_release_gpu_storage(struct nv04_resource *buf) buf->domain = 0; } -static INLINE boolean +static inline bool nouveau_buffer_reallocate(struct nouveau_screen *screen, struct nv04_resource *buf, unsigned domain) { @@ -139,13 +134,13 @@ nouveau_buffer_destroy(struct pipe_screen *pscreen, */ static uint8_t * nouveau_transfer_staging(struct nouveau_context *nv, - struct nouveau_transfer *tx, boolean permit_pb) + struct nouveau_transfer *tx, bool permit_pb) { const unsigned adj = tx->base.box.x & NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK; const unsigned size = align(tx->base.box.width, 4) + adj; if (!nv->push_data) - permit_pb = FALSE; + permit_pb = false; if ((size <= NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD) && permit_pb) { tx->map = align_malloc(size, NOUVEAU_MIN_BUFFER_MAP_ALIGN); @@ -167,7 +162,7 @@ nouveau_transfer_staging(struct nouveau_context *nv, * buffer. Also updates buf->data if present. * * Maybe just migrate to GART right away if we actually need to do this. */ -static boolean +static bool nouveau_transfer_read(struct nouveau_context *nv, struct nouveau_transfer *tx) { struct nv04_resource *buf = nv04_resource(tx->base.resource); @@ -180,12 +175,12 @@ nouveau_transfer_read(struct nouveau_context *nv, struct nouveau_transfer *tx) buf->bo, buf->offset + base, buf->domain, size); if (nouveau_bo_wait(tx->bo, NOUVEAU_BO_RD, nv->client)) - return FALSE; + return false; if (buf->data) memcpy(buf->data + base, tx->map, size); - return TRUE; + return true; } static void @@ -195,7 +190,7 @@ nouveau_transfer_write(struct nouveau_context *nv, struct nouveau_transfer *tx, struct nv04_resource *buf = nv04_resource(tx->base.resource); uint8_t *data = tx->map + offset; const unsigned base = tx->base.box.x + offset; - const boolean can_cb = !((base | size) & 3); + const bool can_cb = !((base | size) & 3); if (buf->data) memcpy(data, buf->data + base, size); @@ -224,32 +219,32 @@ nouveau_transfer_write(struct nouveau_context *nv, struct nouveau_transfer *tx, /* Does a CPU wait for the buffer's backing data to become reliably accessible * for write/read by waiting on the buffer's relevant fences. */ -static INLINE boolean +static inline bool nouveau_buffer_sync(struct nv04_resource *buf, unsigned rw) { if (rw == PIPE_TRANSFER_READ) { if (!buf->fence_wr) - return TRUE; + return true; NOUVEAU_DRV_STAT_RES(buf, buf_non_kernel_fence_sync_count, !nouveau_fence_signalled(buf->fence_wr)); if (!nouveau_fence_wait(buf->fence_wr)) - return FALSE; + return false; } else { if (!buf->fence) - return TRUE; + return true; NOUVEAU_DRV_STAT_RES(buf, buf_non_kernel_fence_sync_count, !nouveau_fence_signalled(buf->fence)); if (!nouveau_fence_wait(buf->fence)) - return FALSE; + return false; nouveau_fence_ref(NULL, &buf->fence); } nouveau_fence_ref(NULL, &buf->fence_wr); - return TRUE; + return true; } -static INLINE boolean +static inline bool nouveau_buffer_busy(struct nv04_resource *buf, unsigned rw) { if (rw == PIPE_TRANSFER_READ) @@ -258,7 +253,7 @@ nouveau_buffer_busy(struct nv04_resource *buf, unsigned rw) return (buf->fence && !nouveau_fence_signalled(buf->fence)); } -static INLINE void +static inline void nouveau_buffer_transfer_init(struct nouveau_transfer *tx, struct pipe_resource *resource, const struct pipe_box *box, @@ -280,7 +275,7 @@ nouveau_buffer_transfer_init(struct nouveau_transfer *tx, tx->map = NULL; } -static INLINE void +static inline void nouveau_buffer_transfer_del(struct nouveau_context *nv, struct nouveau_transfer *tx) { @@ -297,11 +292,11 @@ nouveau_buffer_transfer_del(struct nouveau_context *nv, } /* Creates a cache in system memory of the buffer data. */ -static boolean +static bool nouveau_buffer_cache(struct nouveau_context *nv, struct nv04_resource *buf) { struct nouveau_transfer tx; - boolean ret; + bool ret; tx.base.resource = &buf->base; tx.base.box.x = 0; tx.base.box.width = buf->base.width0; @@ -310,13 +305,13 @@ nouveau_buffer_cache(struct nouveau_context *nv, struct nv04_resource *buf) if (!buf->data) if (!nouveau_buffer_malloc(buf)) - return FALSE; + return false; if (!(buf->status & NOUVEAU_BUFFER_STATUS_DIRTY)) - return TRUE; + return true; nv->stats.buf_cache_count++; - if (!nouveau_transfer_staging(nv, &tx, FALSE)) - return FALSE; + if (!nouveau_transfer_staging(nv, &tx, false)) + return false; ret = nouveau_transfer_read(nv, &tx); if (ret) { @@ -335,15 +330,15 @@ nouveau_buffer_cache(struct nouveau_context *nv, struct nv04_resource *buf) * resource. This can be useful if we would otherwise have to wait for a read * operation to complete on this data. */ -static INLINE boolean +static inline bool nouveau_buffer_should_discard(struct nv04_resource *buf, unsigned usage) { if (!(usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)) - return FALSE; + return false; if (unlikely(buf->base.bind & PIPE_BIND_SHARED)) - return FALSE; + return false; if (unlikely(usage & PIPE_TRANSFER_PERSISTENT)) - return FALSE; + return false; return buf->mm && nouveau_buffer_busy(buf, PIPE_TRANSFER_WRITE); } @@ -413,7 +408,7 @@ nouveau_buffer_transfer_map(struct pipe_context *pipe, * back into VRAM on unmap. */ if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) buf->status &= NOUVEAU_BUFFER_STATUS_REALLOC_MASK; - nouveau_transfer_staging(nv, tx, TRUE); + nouveau_transfer_staging(nv, tx, true); } else { if (buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { /* The GPU is currently writing to this buffer. Copy its current @@ -424,13 +419,13 @@ nouveau_buffer_transfer_map(struct pipe_context *pipe, align_free(buf->data); buf->data = NULL; } - nouveau_transfer_staging(nv, tx, FALSE); + nouveau_transfer_staging(nv, tx, false); nouveau_transfer_read(nv, tx); } else { /* The buffer is currently idle. Create a staging area for writes, * and make sure that the cached data is up-to-date. */ if (usage & PIPE_TRANSFER_WRITE) - nouveau_transfer_staging(nv, tx, TRUE); + nouveau_transfer_staging(nv, tx, true); if (!buf->data) nouveau_buffer_cache(nv, buf); } @@ -482,7 +477,7 @@ nouveau_buffer_transfer_map(struct pipe_context *pipe, if (usage & PIPE_TRANSFER_DISCARD_RANGE) { /* The whole range is being discarded, so it doesn't matter what was * there before. No need to copy anything over. */ - nouveau_transfer_staging(nv, tx, TRUE); + nouveau_transfer_staging(nv, tx, true); map = tx->map; } else if (nouveau_buffer_busy(buf, PIPE_TRANSFER_READ)) { @@ -493,7 +488,7 @@ nouveau_buffer_transfer_map(struct pipe_context *pipe, } else { /* It is expected that the returned buffer be a representation of the * data in question, so we must copy it over from the buffer. */ - nouveau_transfer_staging(nv, tx, TRUE); + nouveau_transfer_staging(nv, tx, true); if (tx->map) memcpy(tx->map, map, box->width); map = tx->map; @@ -544,7 +539,7 @@ nouveau_buffer_transfer_unmap(struct pipe_context *pipe, const uint8_t bind = buf->base.bind; /* make sure we invalidate dedicated caches */ if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) - nv->vbo_dirty = TRUE; + nv->vbo_dirty = true; } util_range_add(&buf->valid_buffer_range, @@ -639,7 +634,7 @@ nouveau_buffer_create(struct pipe_screen *pscreen, { struct nouveau_screen *screen = nouveau_screen(pscreen); struct nv04_resource *buffer; - boolean ret; + bool ret; buffer = CALLOC_STRUCT(nv04_resource); if (!buffer) @@ -683,7 +678,7 @@ nouveau_buffer_create(struct pipe_screen *pscreen, } ret = nouveau_buffer_allocate(screen, buffer, buffer->domain); - if (ret == FALSE) + if (ret == false) goto fail; if (buffer->domain == NOUVEAU_BO_VRAM && screen->hint_buf_keep_sysmem_copy) @@ -730,20 +725,20 @@ nouveau_user_buffer_create(struct pipe_screen *pscreen, void *ptr, return &buffer->base; } -static INLINE boolean +static inline bool nouveau_buffer_data_fetch(struct nouveau_context *nv, struct nv04_resource *buf, struct nouveau_bo *bo, unsigned offset, unsigned size) { if (!nouveau_buffer_malloc(buf)) - return FALSE; + return false; if (nouveau_bo_map(bo, NOUVEAU_BO_RD, nv->client)) - return FALSE; + return false; memcpy(buf->data, (uint8_t *)bo->map + offset, size); - return TRUE; + return true; } /* Migrate a linear buffer (vertex, index, constants) USER -> GART -> VRAM. */ -boolean +bool nouveau_buffer_migrate(struct nouveau_context *nv, struct nv04_resource *buf, const unsigned new_domain) { @@ -758,7 +753,7 @@ nouveau_buffer_migrate(struct nouveau_context *nv, if (new_domain == NOUVEAU_BO_GART && old_domain == 0) { if (!nouveau_buffer_allocate(screen, buf, new_domain)) - return FALSE; + return false; ret = nouveau_bo_map(buf->bo, 0, nv->client); if (ret) return ret; @@ -771,7 +766,7 @@ nouveau_buffer_migrate(struct nouveau_context *nv, if (new_domain == NOUVEAU_BO_VRAM) { /* keep a system memory copy of our data in case we hit a fallback */ if (!nouveau_buffer_data_fetch(nv, buf, buf->bo, buf->offset, size)) - return FALSE; + return false; if (nouveau_mesa_debug) debug_printf("migrating %u KiB to VRAM\n", size / 1024); } @@ -792,28 +787,28 @@ nouveau_buffer_migrate(struct nouveau_context *nv, if (new_domain == NOUVEAU_BO_VRAM && old_domain == 0) { struct nouveau_transfer tx; if (!nouveau_buffer_allocate(screen, buf, NOUVEAU_BO_VRAM)) - return FALSE; + return false; tx.base.resource = &buf->base; tx.base.box.x = 0; tx.base.box.width = buf->base.width0; tx.bo = NULL; tx.map = NULL; - if (!nouveau_transfer_staging(nv, &tx, FALSE)) - return FALSE; + if (!nouveau_transfer_staging(nv, &tx, false)) + return false; nouveau_transfer_write(nv, &tx, 0, tx.base.box.width); nouveau_buffer_transfer_del(nv, &tx); } else - return FALSE; + return false; assert(buf->domain == new_domain); - return TRUE; + return true; } /* Migrate data from glVertexAttribPointer(non-VBO) user buffers to GART. * We'd like to only allocate @size bytes here, but then we'd have to rebase * the vertex indices ... */ -boolean +bool nouveau_user_buffer_upload(struct nouveau_context *nv, struct nv04_resource *buf, unsigned base, unsigned size) @@ -825,20 +820,20 @@ nouveau_user_buffer_upload(struct nouveau_context *nv, buf->base.width0 = base + size; if (!nouveau_buffer_reallocate(screen, buf, NOUVEAU_BO_GART)) - return FALSE; + return false; ret = nouveau_bo_map(buf->bo, 0, nv->client); if (ret) - return FALSE; + return false; memcpy((uint8_t *)buf->bo->map + buf->offset + base, buf->data + base, size); - return TRUE; + return true; } /* Scratch data allocation. */ -static INLINE int +static inline int nouveau_scratch_bo_alloc(struct nouveau_context *nv, struct nouveau_bo **pbo, unsigned size) { @@ -875,7 +870,7 @@ nouveau_scratch_runout_release(struct nouveau_context *nv) /* Allocate an extra bo if we can't fit everything we need simultaneously. * (Could happen for very large user arrays.) */ -static INLINE boolean +static inline bool nouveau_scratch_runout(struct nouveau_context *nv, unsigned size) { int ret; @@ -909,7 +904,7 @@ nouveau_scratch_runout(struct nouveau_context *nv, unsigned size) /* Continue to next scratch buffer, if available (no wrapping, large enough). * Allocate it if it has not yet been created. */ -static INLINE boolean +static inline bool nouveau_scratch_next(struct nouveau_context *nv, unsigned size) { struct nouveau_bo *bo; @@ -917,14 +912,14 @@ nouveau_scratch_next(struct nouveau_context *nv, unsigned size) const unsigned i = (nv->scratch.id + 1) % NOUVEAU_MAX_SCRATCH_BUFS; if ((size > nv->scratch.bo_size) || (i == nv->scratch.wrap)) - return FALSE; + return false; nv->scratch.id = i; bo = nv->scratch.bo[i]; if (!bo) { ret = nouveau_scratch_bo_alloc(nv, &bo, nv->scratch.bo_size); if (ret) - return FALSE; + return false; nv->scratch.bo[i] = bo; } nv->scratch.current = bo; @@ -937,10 +932,10 @@ nouveau_scratch_next(struct nouveau_context *nv, unsigned size) return !ret; } -static boolean +static bool nouveau_scratch_more(struct nouveau_context *nv, unsigned min_size) { - boolean ret; + bool ret; ret = nouveau_scratch_next(nv, min_size); if (!ret) diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.h b/src/gallium/drivers/nouveau/nouveau_buffer.h index de77f481da3..7e6a6cc804b 100644 --- a/src/gallium/drivers/nouveau/nouveau_buffer.h +++ b/src/gallium/drivers/nouveau/nouveau_buffer.h @@ -58,7 +58,7 @@ nouveau_copy_buffer(struct nouveau_context *, struct nv04_resource *dst, unsigned dst_pos, struct nv04_resource *src, unsigned src_pos, unsigned size); -boolean +bool nouveau_buffer_migrate(struct nouveau_context *, struct nv04_resource *, unsigned domain); @@ -66,20 +66,20 @@ void * nouveau_resource_map_offset(struct nouveau_context *, struct nv04_resource *, uint32_t offset, uint32_t flags); -static INLINE void +static inline void nouveau_resource_unmap(struct nv04_resource *res) { /* no-op */ } -static INLINE struct nv04_resource * +static inline struct nv04_resource * nv04_resource(struct pipe_resource *resource) { return (struct nv04_resource *)resource; } /* is resource mapped into the GPU's address space (i.e. VRAM or GART) ? */ -static INLINE boolean +static inline bool nouveau_resource_mapped_by_gpu(struct pipe_resource *resource) { return nv04_resource(resource)->domain != 0; @@ -93,7 +93,7 @@ struct pipe_resource * nouveau_user_buffer_create(struct pipe_screen *screen, void *ptr, unsigned bytes, unsigned usage); -boolean +bool nouveau_user_buffer_upload(struct nouveau_context *, struct nv04_resource *, unsigned base, unsigned size); diff --git a/src/gallium/drivers/nouveau/nouveau_context.h b/src/gallium/drivers/nouveau/nouveau_context.h index c2ba0159afe..24deb7ee4c0 100644 --- a/src/gallium/drivers/nouveau/nouveau_context.h +++ b/src/gallium/drivers/nouveau/nouveau_context.h @@ -13,7 +13,7 @@ struct nouveau_context { struct nouveau_client *client; struct nouveau_pushbuf *pushbuf; - boolean vbo_dirty; + bool vbo_dirty; void (*copy_data)(struct nouveau_context *, struct nouveau_bo *dst, unsigned, unsigned, @@ -53,7 +53,7 @@ struct nouveau_context { } stats; }; -static INLINE struct nouveau_context * +static inline struct nouveau_context * nouveau_context(struct pipe_context *pipe) { return (struct nouveau_context *)pipe; @@ -69,7 +69,7 @@ nouveau_scratch_runout_release(struct nouveau_context *); * because we don't want to un-bo_ref each allocation every time. This is less * work, and we need the wrap index anyway for extreme situations. */ -static INLINE void +static inline void nouveau_scratch_done(struct nouveau_context *nv) { nv->scratch.wrap = nv->scratch.id; @@ -84,7 +84,7 @@ void * nouveau_scratch_get(struct nouveau_context *, unsigned size, uint64_t *gpu_addr, struct nouveau_bo **); -static INLINE void +static inline void nouveau_context_destroy(struct nouveau_context *ctx) { int i; @@ -96,7 +96,7 @@ nouveau_context_destroy(struct nouveau_context *ctx) FREE(ctx); } -static INLINE void +static inline void nouveau_context_update_frame_stats(struct nouveau_context *nv) { nv->stats.buf_cache_frame <<= 1; @@ -104,7 +104,7 @@ nouveau_context_update_frame_stats(struct nouveau_context *nv) nv->stats.buf_cache_count = 0; nv->stats.buf_cache_frame |= 1; if ((nv->stats.buf_cache_frame & 0xf) == 0xf) - nv->screen->hint_buf_keep_sysmem_copy = TRUE; + nv->screen->hint_buf_keep_sysmem_copy = true; } } diff --git a/src/gallium/drivers/nouveau/nouveau_fence.c b/src/gallium/drivers/nouveau/nouveau_fence.c index 17a5174594d..abcdb479954 100644 --- a/src/gallium/drivers/nouveau/nouveau_fence.c +++ b/src/gallium/drivers/nouveau/nouveau_fence.c @@ -28,13 +28,13 @@ #include <sched.h> #endif -boolean +bool nouveau_fence_new(struct nouveau_screen *screen, struct nouveau_fence **fence, - boolean emit) + bool emit) { *fence = CALLOC_STRUCT(nouveau_fence); if (!*fence) - return FALSE; + return false; (*fence)->screen = screen; (*fence)->ref = 1; @@ -43,7 +43,7 @@ nouveau_fence_new(struct nouveau_screen *screen, struct nouveau_fence **fence, if (emit) nouveau_fence_emit(*fence); - return TRUE; + return true; } static void @@ -58,7 +58,7 @@ nouveau_fence_trigger_work(struct nouveau_fence *fence) } } -boolean +bool nouveau_fence_work(struct nouveau_fence *fence, void (*func)(void *), void *data) { @@ -66,16 +66,16 @@ nouveau_fence_work(struct nouveau_fence *fence, if (!fence || fence->state == NOUVEAU_FENCE_STATE_SIGNALLED) { func(data); - return TRUE; + return true; } work = CALLOC_STRUCT(nouveau_fence_work); if (!work) - return FALSE; + return false; work->func = func; work->data = data; LIST_ADD(&work->list, &fence->work); - return TRUE; + return true; } void @@ -132,7 +132,7 @@ nouveau_fence_del(struct nouveau_fence *fence) } void -nouveau_fence_update(struct nouveau_screen *screen, boolean flushed) +nouveau_fence_update(struct nouveau_screen *screen, bool flushed) { struct nouveau_fence *fence; struct nouveau_fence *next = NULL; @@ -167,21 +167,21 @@ nouveau_fence_update(struct nouveau_screen *screen, boolean flushed) #define NOUVEAU_FENCE_MAX_SPINS (1 << 31) -boolean +bool nouveau_fence_signalled(struct nouveau_fence *fence) { struct nouveau_screen *screen = fence->screen; if (fence->state == NOUVEAU_FENCE_STATE_SIGNALLED) - return TRUE; + return true; if (fence->state >= NOUVEAU_FENCE_STATE_EMITTED) - nouveau_fence_update(screen, FALSE); + nouveau_fence_update(screen, false); return fence->state == NOUVEAU_FENCE_STATE_SIGNALLED; } -boolean +bool nouveau_fence_wait(struct nouveau_fence *fence) { struct nouveau_screen *screen = fence->screen; @@ -195,16 +195,16 @@ nouveau_fence_wait(struct nouveau_fence *fence) if (fence->state < NOUVEAU_FENCE_STATE_FLUSHED) if (nouveau_pushbuf_kick(screen->pushbuf, screen->pushbuf->channel)) - return FALSE; + return false; if (fence == screen->fence.current) nouveau_fence_next(screen); do { - nouveau_fence_update(screen, FALSE); + nouveau_fence_update(screen, false); if (fence->state == NOUVEAU_FENCE_STATE_SIGNALLED) - return TRUE; + return true; if (!spins) NOUVEAU_DRV_STAT(screen, any_non_kernel_fence_sync_count, 1); spins++; @@ -218,7 +218,7 @@ nouveau_fence_wait(struct nouveau_fence *fence) fence->sequence, screen->fence.sequence_ack, screen->fence.sequence); - return FALSE; + return false; } void @@ -229,5 +229,5 @@ nouveau_fence_next(struct nouveau_screen *screen) nouveau_fence_ref(NULL, &screen->fence.current); - nouveau_fence_new(screen, &screen->fence.current, FALSE); + nouveau_fence_new(screen, &screen->fence.current, false); } diff --git a/src/gallium/drivers/nouveau/nouveau_fence.h b/src/gallium/drivers/nouveau/nouveau_fence.h index 7bb132a5d15..a1587051b0f 100644 --- a/src/gallium/drivers/nouveau/nouveau_fence.h +++ b/src/gallium/drivers/nouveau/nouveau_fence.h @@ -29,15 +29,15 @@ struct nouveau_fence { void nouveau_fence_emit(struct nouveau_fence *); void nouveau_fence_del(struct nouveau_fence *); -boolean nouveau_fence_new(struct nouveau_screen *, struct nouveau_fence **, - boolean emit); -boolean nouveau_fence_work(struct nouveau_fence *, void (*)(void *), void *); -void nouveau_fence_update(struct nouveau_screen *, boolean flushed); -void nouveau_fence_next(struct nouveau_screen *); -boolean nouveau_fence_wait(struct nouveau_fence *); -boolean nouveau_fence_signalled(struct nouveau_fence *); - -static INLINE void +bool nouveau_fence_new(struct nouveau_screen *, struct nouveau_fence **, + bool emit); +bool nouveau_fence_work(struct nouveau_fence *, void (*)(void *), void *); +void nouveau_fence_update(struct nouveau_screen *, bool flushed); +void nouveau_fence_next(struct nouveau_screen *); +bool nouveau_fence_wait(struct nouveau_fence *); +bool nouveau_fence_signalled(struct nouveau_fence *); + +static inline void nouveau_fence_ref(struct nouveau_fence *fence, struct nouveau_fence **ref) { if (fence) @@ -51,7 +51,7 @@ nouveau_fence_ref(struct nouveau_fence *fence, struct nouveau_fence **ref) *ref = fence; } -static INLINE struct nouveau_fence * +static inline struct nouveau_fence * nouveau_fence(struct pipe_fence_handle *fence) { return (struct nouveau_fence *)fence; diff --git a/src/gallium/drivers/nouveau/nouveau_gldefs.h b/src/gallium/drivers/nouveau/nouveau_gldefs.h index ff97aaa9af0..1538c7b6e57 100644 --- a/src/gallium/drivers/nouveau/nouveau_gldefs.h +++ b/src/gallium/drivers/nouveau/nouveau_gldefs.h @@ -1,7 +1,7 @@ #ifndef __NOUVEAU_GLDEFS_H__ #define __NOUVEAU_GLDEFS_H__ -static INLINE unsigned +static inline unsigned nvgl_blend_func(unsigned factor) { switch (factor) { @@ -40,7 +40,7 @@ nvgl_blend_func(unsigned factor) } } -static INLINE unsigned +static inline unsigned nvgl_blend_eqn(unsigned func) { switch (func) { @@ -59,7 +59,7 @@ nvgl_blend_eqn(unsigned func) } } -static INLINE unsigned +static inline unsigned nvgl_logicop_func(unsigned func) { switch (func) { @@ -100,7 +100,7 @@ nvgl_logicop_func(unsigned func) } } -static INLINE unsigned +static inline unsigned nvgl_comparison_op(unsigned op) { switch (op) { @@ -125,7 +125,7 @@ nvgl_comparison_op(unsigned op) } } -static INLINE unsigned +static inline unsigned nvgl_polygon_mode(unsigned mode) { switch (mode) { @@ -140,7 +140,7 @@ nvgl_polygon_mode(unsigned mode) } } -static INLINE unsigned +static inline unsigned nvgl_stencil_op(unsigned op) { switch (op) { @@ -165,7 +165,7 @@ nvgl_stencil_op(unsigned op) } } -static INLINE unsigned +static inline unsigned nvgl_primitive(unsigned prim) { switch (prim) { case PIPE_PRIM_POINTS: diff --git a/src/gallium/drivers/nouveau/nouveau_mm.c b/src/gallium/drivers/nouveau/nouveau_mm.c index 9c454c56db0..43b3d99f48a 100644 --- a/src/gallium/drivers/nouveau/nouveau_mm.c +++ b/src/gallium/drivers/nouveau/nouveau_mm.c @@ -70,7 +70,7 @@ mm_slab_alloc(struct mm_slab *slab) return -1; } -static INLINE void +static inline void mm_slab_free(struct mm_slab *slab, int i) { assert(i < slab->count); @@ -79,7 +79,7 @@ mm_slab_free(struct mm_slab *slab, int i) assert(slab->free <= slab->count); } -static INLINE int +static inline int mm_get_order(uint32_t size) { int s = __builtin_clz(size) ^ 31; @@ -104,7 +104,7 @@ mm_bucket_by_size(struct nouveau_mman *cache, unsigned size) } /* size of bo allocation for slab with chunks of (1 << chunk_order) bytes */ -static INLINE uint32_t +static inline uint32_t mm_default_slab_size(unsigned chunk_order) { static const int8_t slab_order[MM_MAX_ORDER - MM_MIN_ORDER + 1] = @@ -263,7 +263,7 @@ nouveau_mm_create(struct nouveau_device *dev, uint32_t domain, return cache; } -static INLINE void +static inline void nouveau_mm_free_slabs(struct list_head *head) { struct mm_slab *slab, *next; diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c index c6e5074db19..b2290e7e784 100644 --- a/src/gallium/drivers/nouveau/nouveau_screen.c +++ b/src/gallium/drivers/nouveau/nouveau_screen.c @@ -68,17 +68,13 @@ nouveau_screen_fence_ref(struct pipe_screen *pscreen, } static boolean -nouveau_screen_fence_signalled(struct pipe_screen *screen, - struct pipe_fence_handle *pfence) -{ - return nouveau_fence_signalled(nouveau_fence(pfence)); -} - -static boolean nouveau_screen_fence_finish(struct pipe_screen *screen, struct pipe_fence_handle *pfence, uint64_t timeout) { + if (!timeout) + return nouveau_fence_signalled(nouveau_fence(pfence)); + return nouveau_fence_wait(nouveau_fence(pfence)); } @@ -115,7 +111,7 @@ nouveau_screen_bo_from_handle(struct pipe_screen *pscreen, } -boolean +bool nouveau_screen_bo_get_handle(struct pipe_screen *pscreen, struct nouveau_bo *bo, unsigned stride, @@ -127,11 +123,11 @@ nouveau_screen_bo_get_handle(struct pipe_screen *pscreen, return nouveau_bo_name_get(bo, &whandle->handle) == 0; } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { whandle->handle = bo->handle; - return TRUE; + return true; } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { return nouveau_bo_set_prime(bo, (int *)&whandle->handle) == 0; } else { - return FALSE; + return false; } } @@ -203,7 +199,6 @@ nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev) pscreen->get_timestamp = nouveau_screen_get_timestamp; pscreen->fence_reference = nouveau_screen_fence_ref; - pscreen->fence_signalled = nouveau_screen_fence_signalled; pscreen->fence_finish = nouveau_screen_fence_finish; util_format_s3tc_init(); @@ -214,7 +209,8 @@ nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev) PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_CURSOR | PIPE_BIND_SAMPLER_VIEW | - PIPE_BIND_SHADER_RESOURCE | PIPE_BIND_COMPUTE_RESOURCE | + PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE | + PIPE_BIND_COMPUTE_RESOURCE | PIPE_BIND_GLOBAL; screen->sysmem_bindings = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_STREAM_OUTPUT | diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h b/src/gallium/drivers/nouveau/nouveau_screen.h index 30041b271c9..4fdde9fbf3d 100644 --- a/src/gallium/drivers/nouveau/nouveau_screen.h +++ b/src/gallium/drivers/nouveau/nouveau_screen.h @@ -49,7 +49,7 @@ struct nouveau_screen { int64_t cpu_gpu_time_delta; - boolean hint_buf_keep_sysmem_copy; + bool hint_buf_keep_sysmem_copy; unsigned vram_domain; @@ -112,15 +112,15 @@ struct nouveau_screen { # define NOUVEAU_DRV_STAT_IFD(x) #endif -static INLINE struct nouveau_screen * +static inline struct nouveau_screen * nouveau_screen(struct pipe_screen *pscreen) { return (struct nouveau_screen *)pscreen; } -boolean nouveau_drm_screen_unref(struct nouveau_screen *screen); +bool nouveau_drm_screen_unref(struct nouveau_screen *screen); -boolean +bool nouveau_screen_bo_get_handle(struct pipe_screen *pscreen, struct nouveau_bo *bo, unsigned stride, diff --git a/src/gallium/drivers/nouveau/nouveau_statebuf.h b/src/gallium/drivers/nouveau/nouveau_statebuf.h index 4f8bd7bdf16..f38014091ba 100644 --- a/src/gallium/drivers/nouveau/nouveau_statebuf.h +++ b/src/gallium/drivers/nouveau/nouveau_statebuf.h @@ -20,7 +20,7 @@ struct nouveau_statebuf_builder #define sb_data(sb, v) *(sb).p++ = (v) #endif -static INLINE uint32_t sb_header(unsigned subc, unsigned mthd, unsigned size) +static inline uint32_t sb_header(unsigned subc, unsigned mthd, unsigned size) { return (size << 18) | (subc << 13) | mthd; } diff --git a/src/gallium/drivers/nouveau/nouveau_video.c b/src/gallium/drivers/nouveau/nouveau_video.c index d6330fa63a8..e414a534418 100644 --- a/src/gallium/drivers/nouveau/nouveau_video.c +++ b/src/gallium/drivers/nouveau/nouveau_video.c @@ -100,7 +100,7 @@ nouveau_vpe_fini(struct nouveau_decoder *dec) { dec->current = dec->future = dec->past = 8; } -static INLINE void +static inline void nouveau_vpe_mb_dct_blocks(struct nouveau_decoder *dec, const struct pipe_mpeg12_macroblock *mb) { int cbb; @@ -125,7 +125,7 @@ nouveau_vpe_mb_dct_blocks(struct nouveau_decoder *dec, const struct pipe_mpeg12_ } } -static INLINE void +static inline void nouveau_vpe_mb_data_blocks(struct nouveau_decoder *dec, const struct pipe_mpeg12_macroblock *mb) { int cbb; @@ -143,7 +143,7 @@ nouveau_vpe_mb_data_blocks(struct nouveau_decoder *dec, const struct pipe_mpeg12 } } -static INLINE void +static inline void nouveau_vpe_mb_dct_header(struct nouveau_decoder *dec, const struct pipe_mpeg12_macroblock *mb, bool luma) @@ -187,7 +187,7 @@ nouveau_vpe_mb_dct_header(struct nouveau_decoder *dec, x | (y << NV17_MPEG_CMD_MB_COORDS_Y__SHIFT)); } -static INLINE unsigned int +static inline unsigned int nouveau_vpe_mb_mv_flags(bool luma, int mv_h, int mv_v, bool forward, bool first, bool vert) { unsigned mc_header = 0; @@ -228,7 +228,7 @@ static int div_up(int val, int mult) { return val / mult; } -static INLINE void +static inline void nouveau_vpe_mb_mv(struct nouveau_decoder *dec, unsigned mc_header, bool luma, bool frame, bool forward, bool vert, int x, int y, const short motions[2], @@ -296,16 +296,16 @@ nouveau_vpe_mb_mv_header(struct nouveau_decoder *dec, case PIPE_MPEG12_MO_TYPE_DUAL_PRIME: { base = NV17_MPEG_CMD_CHROMA_MV_HEADER_COUNT_2; if (forward) { - nouveau_vpe_mb_mv(dec, base, luma, frame, TRUE, FALSE, - x, y, mb->PMV[0][0], dec->past, TRUE); - nouveau_vpe_mb_mv(dec, base, luma, frame, TRUE, TRUE, - x, y2, mb->PMV[0][0], dec->past, FALSE); + nouveau_vpe_mb_mv(dec, base, luma, frame, true, false, + x, y, mb->PMV[0][0], dec->past, true); + nouveau_vpe_mb_mv(dec, base, luma, frame, true, true, + x, y2, mb->PMV[0][0], dec->past, false); } if (backward && forward) { - nouveau_vpe_mb_mv(dec, base, luma, frame, !forward, TRUE, - x, y, mb->PMV[1][0], dec->future, TRUE); - nouveau_vpe_mb_mv(dec, base, luma, frame, !forward, FALSE, - x, y2, mb->PMV[1][1], dec->future, FALSE); + nouveau_vpe_mb_mv(dec, base, luma, frame, !forward, true, + x, y, mb->PMV[1][0], dec->future, true); + nouveau_vpe_mb_mv(dec, base, luma, frame, !forward, false, + x, y2, mb->PMV[1][1], dec->future, false); } else assert(!backward); break; } @@ -320,13 +320,13 @@ nouveau_vpe_mb_mv_header(struct nouveau_decoder *dec, if (frame) base |= NV17_MPEG_CMD_CHROMA_MV_HEADER_TYPE_FRAME; if (forward) - nouveau_vpe_mb_mv(dec, base, luma, frame, TRUE, + nouveau_vpe_mb_mv(dec, base, luma, frame, true, dec->picture_structure != PIPE_MPEG12_PICTURE_STRUCTURE_FIELD_TOP, - x, y, mb->PMV[0][0], dec->past, TRUE); + x, y, mb->PMV[0][0], dec->past, true); if (backward && forward) - nouveau_vpe_mb_mv(dec, base, luma, frame, FALSE, + nouveau_vpe_mb_mv(dec, base, luma, frame, false, dec->picture_structure == PIPE_MPEG12_PICTURE_STRUCTURE_FIELD_TOP, - x, y, mb->PMV[0][1], dec->future, TRUE); + x, y, mb->PMV[0][1], dec->future, true); else assert(!backward); break; } @@ -341,11 +341,11 @@ mv1: base |= NV17_MPEG_CMD_CHROMA_MV_HEADER_TYPE_FRAME; /* frame 16x16 */ if (forward) - nouveau_vpe_mb_mv(dec, base, luma, frame, TRUE, FALSE, - x, y, mb->PMV[0][0], dec->past, TRUE); + nouveau_vpe_mb_mv(dec, base, luma, frame, true, false, + x, y, mb->PMV[0][0], dec->past, true); if (backward) - nouveau_vpe_mb_mv(dec, base, luma, frame, !forward, FALSE, - x, y, mb->PMV[0][1], dec->future, TRUE); + nouveau_vpe_mb_mv(dec, base, luma, frame, !forward, false, + x, y, mb->PMV[0][1], dec->future, true); return; mv2: @@ -353,20 +353,20 @@ mv2: if (!frame) base |= NV17_MPEG_CMD_CHROMA_MV_HEADER_MV_SPLIT_HALF_MB; if (forward) { - nouveau_vpe_mb_mv(dec, base, luma, frame, TRUE, + nouveau_vpe_mb_mv(dec, base, luma, frame, true, mb->motion_vertical_field_select & PIPE_MPEG12_FS_FIRST_FORWARD, - x, y, mb->PMV[0][0], dec->past, TRUE); - nouveau_vpe_mb_mv(dec, base, luma, frame, TRUE, + x, y, mb->PMV[0][0], dec->past, true); + nouveau_vpe_mb_mv(dec, base, luma, frame, true, mb->motion_vertical_field_select & PIPE_MPEG12_FS_SECOND_FORWARD, - x, y2, mb->PMV[1][0], dec->past, FALSE); + x, y2, mb->PMV[1][0], dec->past, false); } if (backward) { nouveau_vpe_mb_mv(dec, base, luma, frame, !forward, mb->motion_vertical_field_select & PIPE_MPEG12_FS_FIRST_BACKWARD, - x, y, mb->PMV[0][1], dec->future, TRUE); + x, y, mb->PMV[0][1], dec->future, true); nouveau_vpe_mb_mv(dec, base, luma, frame, !forward, mb->motion_vertical_field_select & PIPE_MPEG12_FS_SECOND_BACKWARD, - x, y2, mb->PMV[1][1], dec->future, FALSE); + x, y2, mb->PMV[1][1], dec->future, false); } } @@ -438,14 +438,14 @@ nouveau_decoder_decode_macroblock(struct pipe_video_codec *decoder, mb = (const struct pipe_mpeg12_macroblock *)pipe_mb; for (i = 0; i < num_macroblocks; ++i, mb++) { if (mb->macroblock_type & PIPE_MPEG12_MB_TYPE_INTRA) { - nouveau_vpe_mb_dct_header(dec, mb, TRUE); - nouveau_vpe_mb_dct_header(dec, mb, FALSE); + nouveau_vpe_mb_dct_header(dec, mb, true); + nouveau_vpe_mb_dct_header(dec, mb, false); } else { - nouveau_vpe_mb_mv_header(dec, mb, TRUE); - nouveau_vpe_mb_dct_header(dec, mb, TRUE); + nouveau_vpe_mb_mv_header(dec, mb, true); + nouveau_vpe_mb_dct_header(dec, mb, true); - nouveau_vpe_mb_mv_header(dec, mb, FALSE); - nouveau_vpe_mb_dct_header(dec, mb, FALSE); + nouveau_vpe_mb_mv_header(dec, mb, false); + nouveau_vpe_mb_dct_header(dec, mb, false); } if (dec->base.entrypoint <= PIPE_VIDEO_ENTRYPOINT_IDCT) nouveau_vpe_mb_dct_blocks(dec, mb); diff --git a/src/gallium/drivers/nouveau/nouveau_video.h b/src/gallium/drivers/nouveau/nouveau_video.h index 08d48b371fd..fd1bd527deb 100644 --- a/src/gallium/drivers/nouveau/nouveau_video.h +++ b/src/gallium/drivers/nouveau/nouveau_video.h @@ -45,7 +45,7 @@ struct nouveau_decoder { #define NV31_VIDEO_BIND_CMD NV31_MPEG_IMAGE_Y_OFFSET__LEN #define NV31_VIDEO_BIND_COUNT (NV31_MPEG_IMAGE_Y_OFFSET__LEN + 1) -static INLINE void +static inline void nouveau_vpe_write(struct nouveau_decoder *dec, unsigned data) { dec->cmds[dec->ofs++] = data; } @@ -54,33 +54,33 @@ nouveau_vpe_write(struct nouveau_decoder *dec, unsigned data) { #define NV31_MPEG(mthd) SUBC_MPEG(NV31_MPEG_##mthd) #define NV84_MPEG(mthd) SUBC_MPEG(NV84_MPEG_##mthd) -static INLINE uint32_t +static inline uint32_t NV04_FIFO_PKHDR(int subc, int mthd, unsigned size) { return 0x00000000 | (size << 18) | (subc << 13) | mthd; } -static INLINE uint32_t +static inline uint32_t NV04_FIFO_PKHDR_NI(int subc, int mthd, unsigned size) { return 0x40000000 | (size << 18) | (subc << 13) | mthd; } -static INLINE void +static inline void BEGIN_NV04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) { PUSH_SPACE(push, size + 1); PUSH_DATA (push, NV04_FIFO_PKHDR(subc, mthd, size)); } -static INLINE void +static inline void BEGIN_NI04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) { PUSH_SPACE(push, size + 1); PUSH_DATA (push, NV04_FIFO_PKHDR_NI(subc, mthd, size)); } -static INLINE void +static inline void PUSH_MTHDl(struct nouveau_pushbuf *push, int subc, int mthd, struct nouveau_bo *bo, uint32_t offset, struct nouveau_bufctx *ctx, int bin, uint32_t rw) diff --git a/src/gallium/drivers/nouveau/nouveau_vp3_video.h b/src/gallium/drivers/nouveau/nouveau_vp3_video.h index 279a1ce18ef..33e3bef3df3 100644 --- a/src/gallium/drivers/nouveau/nouveau_vp3_video.h +++ b/src/gallium/drivers/nouveau/nouveau_vp3_video.h @@ -135,22 +135,22 @@ struct comm { uint32_t parse_endpos[0x10]; // 1c0 }; -static INLINE uint32_t nouveau_vp3_video_align(uint32_t h) +static inline uint32_t nouveau_vp3_video_align(uint32_t h) { return ((h+0x3f)&~0x3f); }; -static INLINE uint32_t mb(uint32_t coord) +static inline uint32_t mb(uint32_t coord) { return (coord + 0xf)>>4; } -static INLINE uint32_t mb_half(uint32_t coord) +static inline uint32_t mb_half(uint32_t coord) { return (coord + 0x1f)>>5; } -static INLINE uint64_t +static inline uint64_t nouveau_vp3_video_addr(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video_buffer *target) { uint64_t ret; @@ -161,7 +161,7 @@ nouveau_vp3_video_addr(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video return dec->ref_bo->offset + ret; } -static INLINE void +static inline void nouveau_vp3_ycbcr_offsets(struct nouveau_vp3_decoder *dec, uint32_t *y2, uint32_t *cbcr, uint32_t *cbcr2) { @@ -182,7 +182,7 @@ nouveau_vp3_ycbcr_offsets(struct nouveau_vp3_decoder *dec, uint32_t *y2, } } -static INLINE void +static inline void nouveau_vp3_inter_sizes(struct nouveau_vp3_decoder *dec, uint32_t slice_count, uint32_t *slice_size, uint32_t *bucket_size, uint32_t *ring_size) diff --git a/src/gallium/drivers/nouveau/nouveau_winsys.h b/src/gallium/drivers/nouveau/nouveau_winsys.h index 51effb1d8d2..389a229eb78 100644 --- a/src/gallium/drivers/nouveau/nouveau_winsys.h +++ b/src/gallium/drivers/nouveau/nouveau_winsys.h @@ -15,34 +15,34 @@ #define NOUVEAU_MIN_BUFFER_MAP_ALIGN 64 #define NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK (NOUVEAU_MIN_BUFFER_MAP_ALIGN - 1) -static INLINE uint32_t +static inline uint32_t PUSH_AVAIL(struct nouveau_pushbuf *push) { return push->end - push->cur; } -static INLINE boolean +static inline bool PUSH_SPACE(struct nouveau_pushbuf *push, uint32_t size) { if (PUSH_AVAIL(push) < size) return nouveau_pushbuf_space(push, size, 0, 0) == 0; - return TRUE; + return true; } -static INLINE void +static inline void PUSH_DATA(struct nouveau_pushbuf *push, uint32_t data) { *push->cur++ = data; } -static INLINE void +static inline void PUSH_DATAp(struct nouveau_pushbuf *push, const void *data, uint32_t size) { memcpy(push->cur, data, size * 4); push->cur += size; } -static INLINE void +static inline void PUSH_DATAf(struct nouveau_pushbuf *push, float f) { union { float f; uint32_t i; } u; @@ -50,7 +50,7 @@ PUSH_DATAf(struct nouveau_pushbuf *push, float f) PUSH_DATA(push, u.i); } -static INLINE void +static inline void PUSH_KICK(struct nouveau_pushbuf *push) { nouveau_pushbuf_kick(push, push->channel); @@ -60,7 +60,7 @@ PUSH_KICK(struct nouveau_pushbuf *push) #define NOUVEAU_RESOURCE_FLAG_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0) #define NOUVEAU_RESOURCE_FLAG_DRV_PRIV (PIPE_RESOURCE_FLAG_DRV_PRIV << 1) -static INLINE uint32_t +static inline uint32_t nouveau_screen_transfer_flags(unsigned pipe) { uint32_t flags = 0; diff --git a/src/gallium/drivers/nouveau/nv30/nv30-40_3d.xml.h b/src/gallium/drivers/nouveau/nv30/nv30-40_3d.xml.h index 447f4b3b7ae..95468e580dd 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30-40_3d.xml.h +++ b/src/gallium/drivers/nouveau/nv30/nv30-40_3d.xml.h @@ -1459,6 +1459,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV40_3D_VTX_CACHE_INVALIDATE 0x00001714 +#define NV40_3D_VB_ELEMENT_BASE 0x0000173c + #define NV30_3D_VTXFMT(i0) (0x00001740 + 0x4*(i0)) #define NV30_3D_VTXFMT__ESIZE 0x00000004 #define NV30_3D_VTXFMT__LEN 0x00000010 diff --git a/src/gallium/drivers/nouveau/nv30/nv30_clear.c b/src/gallium/drivers/nouveau/nv30/nv30_clear.c index 83fd1fa38dd..118cac77277 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_clear.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_clear.c @@ -32,7 +32,7 @@ #include "nv30/nv30_context.h" #include "nv30/nv30_format.h" -static INLINE uint32_t +static inline uint32_t pack_rgba(enum pipe_format format, const float *rgba) { union util_color uc; @@ -40,7 +40,7 @@ pack_rgba(enum pipe_format format, const float *rgba) return uc.ui[0]; } -static INLINE uint32_t +static inline uint32_t pack_zeta(enum pipe_format format, double depth, unsigned stencil) { uint32_t zuint = (uint32_t)(depth * 4294967295.0); @@ -58,7 +58,7 @@ nv30_clear(struct pipe_context *pipe, unsigned buffers, struct pipe_framebuffer_state *fb = &nv30->framebuffer; uint32_t colr = 0, zeta = 0, mode = 0; - if (!nv30_state_validate(nv30, NV30_NEW_FRAMEBUFFER | NV30_NEW_SCISSOR, TRUE)) + if (!nv30_state_validate(nv30, NV30_NEW_FRAMEBUFFER | NV30_NEW_SCISSOR, true)) return; if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) { diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.c b/src/gallium/drivers/nouveau/nv30/nv30_context.c index 617b0887810..6e88ed725d6 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_context.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_context.c @@ -45,7 +45,7 @@ nv30_context_kick_notify(struct nouveau_pushbuf *push) screen = &nv30->screen->base; nouveau_fence_next(screen); - nouveau_fence_update(screen, TRUE); + nouveau_fence_update(screen, true); if (push->bufctx) { struct nouveau_bufref *bref; @@ -165,6 +165,12 @@ nv30_context_destroy(struct pipe_context *pipe) if (nv30->draw) draw_destroy(nv30->draw); + if (nv30->blit_vp) + nouveau_heap_free(&nv30->blit_vp); + + if (nv30->blit_fp) + pipe_resource_reference(&nv30->blit_fp, NULL); + if (nv30->screen->base.pushbuf->user_priv == &nv30->bufctx) nv30->screen->base.pushbuf->user_priv = NULL; @@ -233,7 +239,7 @@ nv30_context_create(struct pipe_screen *pscreen, void *priv) nv30->config.aniso = NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_OFF; - if (debug_get_bool_option("NV30_SWTNL", FALSE)) + if (debug_get_bool_option("NV30_SWTNL", false)) nv30->draw_flags |= NV30_NEW_SWTNL; nv30->sample_mask = 0xffff; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.h b/src/gallium/drivers/nouveau/nv30/nv30_context.h index 592cdbe24f9..d5c18bb62dc 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_context.h +++ b/src/gallium/drivers/nouveau/nv30/nv30_context.h @@ -51,7 +51,8 @@ struct nv30_context { unsigned rt_enable; unsigned scissor_off; unsigned num_vtxelts; - boolean prim_restart; + int index_bias; + bool prim_restart; struct nv30_fragprog *fragprog; } state; @@ -114,17 +115,17 @@ struct nv30_context { uint32_t vbo_user; unsigned vbo_min_index; unsigned vbo_max_index; - boolean vbo_push_hint; + bool vbo_push_hint; struct nouveau_heap *blit_vp; struct pipe_resource *blit_fp; struct pipe_query *render_cond_query; unsigned render_cond_mode; - boolean render_cond_cond; + bool render_cond_cond; }; -static INLINE struct nv30_context * +static inline struct nv30_context * nv30_context(struct pipe_context *pipe) { return (struct nv30_context *)pipe; @@ -203,8 +204,8 @@ nv30_draw_init(struct pipe_context *pipe); void nv30_render_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info); -boolean -nv30_state_validate(struct nv30_context *nv30, uint32_t mask, boolean hwtnl); +bool +nv30_state_validate(struct nv30_context *nv30, uint32_t mask, bool hwtnl); void nv30_state_release(struct nv30_context *nv30); @@ -213,7 +214,7 @@ nv30_state_release(struct nv30_context *nv30); #define NV30_PRIM_GL_CASE(n) \ case PIPE_PRIM_##n: return NV30_3D_VERTEX_BEGIN_END_##n -static INLINE unsigned +static inline unsigned nv30_prim_gl(unsigned prim) { switch (prim) { diff --git a/src/gallium/drivers/nouveau/nv30/nv30_draw.c b/src/gallium/drivers/nouveau/nv30/nv30_draw.c index c1665b7ad2f..098d6e499fa 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_draw.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_draw.c @@ -52,7 +52,7 @@ struct nv30_render { uint32_t prim; }; -static INLINE struct nv30_render * +static inline struct nv30_render * nv30_render(struct vbuf_render *render) { return (struct nv30_render *)render; @@ -79,12 +79,12 @@ nv30_render_allocate_vertices(struct vbuf_render *render, PIPE_BIND_VERTEX_BUFFER, PIPE_USAGE_STREAM, render->max_vertex_buffer_bytes); if (!r->buffer) - return FALSE; + return false; r->offset = 0; } - return TRUE; + return true; } static void * @@ -134,7 +134,7 @@ nv30_render_draw_elements(struct vbuf_render *render, NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, NV30_3D_VTXBUF_DMA1); } - if (!nv30_state_validate(nv30, ~0, FALSE)) + if (!nv30_state_validate(nv30, ~0, false)) return; BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1); @@ -179,7 +179,7 @@ nv30_render_draw_arrays(struct vbuf_render *render, unsigned start, uint nr) NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, NV30_3D_VTXBUF_DMA1); } - if (!nv30_state_validate(nv30, ~0, FALSE)) + if (!nv30_state_validate(nv30, ~0, false)) return; BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1); @@ -221,7 +221,7 @@ static const struct { [TGSI_SEMANTIC_TEXCOORD] = { EMIT_4F, INTERP_PERSPECTIVE, 8, 7, 0x00004000 }, }; -static boolean +static bool vroute_add(struct nv30_render *r, uint attrib, uint sem, uint *idx) { struct nv30_screen *screen = r->nv30->screen; @@ -245,7 +245,7 @@ vroute_add(struct nv30_render *r, uint attrib, uint sem, uint *idx) } if (emit == EMIT_OMIT) - return FALSE; + return false; draw_emit_vertex_attr(vinfo, emit, vroute[sem].interp, attrib); format = draw_translate_vinfo_format(emit); @@ -272,10 +272,10 @@ vroute_add(struct nv30_render *r, uint attrib, uint sem, uint *idx) assert(sem == TGSI_SEMANTIC_TEXCOORD); *idx = 0x00001000 << (result - 8); } - return TRUE; + return true; } -static boolean +static bool nv30_render_validate(struct nv30_context *nv30) { struct nv30_render *r = nv30_render(nv30->draw->render); @@ -300,7 +300,7 @@ nv30_render_validate(struct nv30_context *nv30) } if (nouveau_heap_alloc(heap, 16, &r->vertprog, &r->vertprog)) - return FALSE; + return false; } } @@ -370,7 +370,7 @@ nv30_render_validate(struct nv30_context *nv30) } vinfo->size /= 4; - return TRUE; + return true; } void @@ -519,6 +519,6 @@ nv30_draw_init(struct pipe_context *pipe) draw_set_rasterize_stage(draw, stage); draw_wide_line_threshold(draw, 10000000.f); draw_wide_point_threshold(draw, 10000000.f); - draw_wide_point_sprites(draw, TRUE); + draw_wide_point_sprites(draw, true); nv30->draw = draw; } diff --git a/src/gallium/drivers/nouveau/nv30/nv30_format.h b/src/gallium/drivers/nouveau/nv30/nv30_format.h index 8bf4a37299f..fa1e922fb65 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_format.h +++ b/src/gallium/drivers/nouveau/nv30/nv30_format.h @@ -27,28 +27,28 @@ struct nv30_texfmt { }; extern const struct nv30_format_info nv30_format_info_table[]; -static INLINE const struct nv30_format_info * +static inline const struct nv30_format_info * nv30_format_info(struct pipe_screen *pscreen, enum pipe_format format) { return &nv30_format_info_table[format]; } extern const struct nv30_format nv30_format_table[]; -static INLINE const struct nv30_format * +static inline const struct nv30_format * nv30_format(struct pipe_screen *pscreen, enum pipe_format format) { return &nv30_format_table[format]; } extern const struct nv30_vtxfmt nv30_vtxfmt_table[]; -static INLINE const struct nv30_vtxfmt * +static inline const struct nv30_vtxfmt * nv30_vtxfmt(struct pipe_screen *pscreen, enum pipe_format format) { return &nv30_vtxfmt_table[format]; } extern const struct nv30_texfmt nv30_texfmt_table[]; -static INLINE const struct nv30_texfmt * +static inline const struct nv30_texfmt * nv30_texfmt(struct pipe_screen *pscreen, enum pipe_format format) { return &nv30_texfmt_table[format]; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c b/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c index 7f227868f73..6de61bcc1c0 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c @@ -37,22 +37,26 @@ nv30_fragprog_upload(struct nv30_context *nv30) struct nouveau_context *nv = &nv30->base; struct nv30_fragprog *fp = nv30->fragprog.program; struct pipe_context *pipe = &nv30->base.pipe; - struct pipe_transfer *transfer; - uint32_t *map; - int i; (void)i; - if (unlikely(!fp->buffer)) { + if (unlikely(!fp->buffer)) fp->buffer = pipe_buffer_create(pipe->screen, 0, 0, fp->insn_len * 4); - } - map = pipe_buffer_map(pipe, fp->buffer, PIPE_TRANSFER_WRITE, &transfer); #ifndef PIPE_ARCH_BIG_ENDIAN - memcpy(map, fp->insn, fp->insn_len * 4); + pipe_buffer_write(pipe, fp->buffer, 0, fp->insn_len * 4, fp->insn); #else - for (i = 0; i < fp->insn_len; i++) - *map++ = (fp->insn[i] >> 16) | (fp->insn[i] << 16); + { + struct pipe_transfer *transfer; + uint32_t *map; + int i; + + map = pipe_buffer_map(pipe, fp->buffer, + PIPE_TRANSFER_WRITE | PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE, + &transfer); + for (i = 0; i < fp->insn_len; i++) + *map++ = (fp->insn[i] >> 16) | (fp->insn[i] << 16); + pipe_buffer_unmap(pipe, transfer); + } #endif - pipe_buffer_unmap(pipe, transfer); if (nv04_resource(fp->buffer)->domain != NOUVEAU_BO_VRAM) nouveau_buffer_migrate(nv, nv04_resource(fp->buffer), NOUVEAU_BO_VRAM); @@ -64,7 +68,7 @@ nv30_fragprog_validate(struct nv30_context *nv30) struct nouveau_pushbuf *push = nv30->base.pushbuf; struct nouveau_object *eng3d = nv30->screen->eng3d; struct nv30_fragprog *fp = nv30->fragprog.program; - boolean upload = FALSE; + bool upload = false; int i; if (!fp->translated) { @@ -72,7 +76,7 @@ nv30_fragprog_validate(struct nv30_context *nv30) if (!fp->translated) return; - upload = TRUE; + upload = true; } /* update constants, also needs to be done on every fp switch as we @@ -89,7 +93,7 @@ nv30_fragprog_validate(struct nv30_context *nv30) if (!memcmp(&fp->insn[off], &cbuf[idx], 4 * 4)) continue; memcpy(&fp->insn[off], &cbuf[idx], 4 * 4); - upload = TRUE; + upload = true; } } @@ -161,8 +165,15 @@ static void nv30_fp_state_bind(struct pipe_context *pipe, void *hwcso) { struct nv30_context *nv30 = nv30_context(pipe); + struct nv30_fragprog *fp = hwcso; + + /* reset the bucftx so that we don't keep a dangling reference to the fp + * code + */ + if (fp != nv30->state.fragprog) + PUSH_RESET(nv30->base.pushbuf, BUFCTX_FRAGPROG); - nv30->fragprog.program = hwcso; + nv30->fragprog.program = fp; nv30->dirty |= NV30_NEW_FRAGPROG; } diff --git a/src/gallium/drivers/nouveau/nv30/nv30_miptree.c b/src/gallium/drivers/nouveau/nv30/nv30_miptree.c index 1a4b8929c0f..c75b4b95fd8 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_miptree.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_miptree.c @@ -33,7 +33,7 @@ #include "nv30/nv30_resource.h" #include "nv30/nv30_transfer.h" -static INLINE unsigned +static inline unsigned layer_offset(struct pipe_resource *pt, unsigned level, unsigned layer) { struct nv30_miptree *mt = nv30_miptree(pt); @@ -54,7 +54,7 @@ nv30_miptree_get_handle(struct pipe_screen *pscreen, unsigned stride; if (!mt || !mt->base.bo) - return FALSE; + return false; stride = mt->level[0].pitch; @@ -78,13 +78,13 @@ struct nv30_transfer { unsigned nblocksy; }; -static INLINE struct nv30_transfer * +static inline struct nv30_transfer * nv30_transfer(struct pipe_transfer *ptx) { return (struct nv30_transfer *)ptx; } -static INLINE void +static inline void define_rect(struct pipe_resource *pt, unsigned level, unsigned z, unsigned x, unsigned y, unsigned w, unsigned h, struct nv30_rect *rect) @@ -242,8 +242,8 @@ nv30_miptree_transfer_map(struct pipe_context *pipe, struct pipe_resource *pt, tx->base.level = level; tx->base.usage = usage; tx->base.box = *box; - tx->base.stride = util_format_get_nblocksx(pt->format, box->width) * - util_format_get_blocksize(pt->format); + tx->base.stride = align(util_format_get_nblocksx(pt->format, box->width) * + util_format_get_blocksize(pt->format), 64); tx->base.layer_stride = util_format_get_nblocksy(pt->format, box->height) * tx->base.stride; @@ -372,7 +372,7 @@ nv30_miptree_create(struct pipe_screen *pscreen, } if (!mt->uniform_pitch) - mt->swizzled = TRUE; + mt->swizzled = true; size = 0; for (l = 0; l <= pt->last_level; l++) { diff --git a/src/gallium/drivers/nouveau/nv30/nv30_push.c b/src/gallium/drivers/nouveau/nv30/nv30_push.c index e0734fa70d3..67ab0508c17 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_push.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_push.c @@ -47,12 +47,12 @@ struct push_context { struct translate *translate; - boolean primitive_restart; + bool primitive_restart; uint32_t prim; uint32_t restart_index; }; -static INLINE unsigned +static inline unsigned prim_restart_search_i08(uint8_t *elts, unsigned push, uint8_t index) { unsigned i; @@ -62,7 +62,7 @@ prim_restart_search_i08(uint8_t *elts, unsigned push, uint8_t index) return i; } -static INLINE unsigned +static inline unsigned prim_restart_search_i16(uint16_t *elts, unsigned push, uint16_t index) { unsigned i; @@ -72,7 +72,7 @@ prim_restart_search_i16(uint16_t *elts, unsigned push, uint16_t index) return i; } -static INLINE unsigned +static inline unsigned prim_restart_search_i32(uint32_t *elts, unsigned push, uint32_t index) { unsigned i; @@ -199,7 +199,7 @@ nv30_push_vbo(struct nv30_context *nv30, const struct pipe_draw_info *info) { struct push_context ctx; unsigned i, index_size; - boolean apply_bias = info->indexed && info->index_bias; + bool apply_bias = info->indexed && info->index_bias; ctx.push = nv30->base.pushbuf; ctx.translate = nv30->vertex->translate; @@ -241,7 +241,7 @@ nv30_push_vbo(struct nv30_context *nv30, const struct pipe_draw_info *info) } else { ctx.idxbuf = NULL; index_size = 0; - ctx.primitive_restart = FALSE; + ctx.primitive_restart = false; ctx.restart_index = 0; } diff --git a/src/gallium/drivers/nouveau/nv30/nv30_query.c b/src/gallium/drivers/nouveau/nv30/nv30_query.c index 516ee83168e..3980be9579a 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_query.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_query.c @@ -98,7 +98,7 @@ struct nv30_query { uint64_t result; }; -static INLINE struct nv30_query * +static inline struct nv30_query * nv30_query(struct pipe_query *pipe) { return (struct nv30_query *)pipe; @@ -208,7 +208,7 @@ nv30_query_result(struct pipe_context *pipe, struct pipe_query *pq, if (ntfy1) { while (ntfy1[3] & 0xff000000) { if (!wait) - return FALSE; + return false; } switch (q->type) { @@ -228,7 +228,7 @@ nv30_query_result(struct pipe_context *pipe, struct pipe_query *pq, } *res64 = q->result; - return TRUE; + return true; } static void diff --git a/src/gallium/drivers/nouveau/nv30/nv30_resource.c b/src/gallium/drivers/nouveau/nv30/nv30_resource.c index 38fac8af898..a98a6464de8 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_resource.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_resource.c @@ -42,12 +42,12 @@ nv30_memory_barrier(struct pipe_context *pipe, unsigned flags) if (!nv30->vtxbuf[i].buffer) continue; if (nv30->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) - nv30->base.vbo_dirty = TRUE; + nv30->base.vbo_dirty = true; } if (nv30->idxbuf.buffer && nv30->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) - nv30->base.vbo_dirty = TRUE; + nv30->base.vbo_dirty = true; } } diff --git a/src/gallium/drivers/nouveau/nv30/nv30_resource.h b/src/gallium/drivers/nouveau/nv30/nv30_resource.h index 1981c8d9ab9..8dac7795c9d 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_resource.h +++ b/src/gallium/drivers/nouveau/nv30/nv30_resource.h @@ -15,7 +15,7 @@ struct nv30_surface { uint16_t depth; }; -static INLINE struct nv30_surface * +static inline struct nv30_surface * nv30_surface(struct pipe_surface *ps) { return (struct nv30_surface *)ps; @@ -32,13 +32,13 @@ struct nv30_miptree { struct nv30_miptree_level level[13]; uint32_t uniform_pitch; uint32_t layer_size; - boolean swizzled; + bool swizzled; unsigned ms_mode; unsigned ms_x:1; unsigned ms_y:1; }; -static INLINE struct nv30_miptree * +static inline struct nv30_miptree * nv30_miptree(struct pipe_resource *pt) { return (struct nv30_miptree *)pt; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index 2e38a1978ae..7aad26ba18b 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -69,6 +69,8 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return PIPE_ENDIAN_LITTLE; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: return 16; + case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: + return NOUVEAU_MIN_BUFFER_MAP_ALIGN; case PIPE_CAP_MAX_VIEWPORTS: return 1; case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: @@ -96,6 +98,9 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return 1; + /* nv35 capabilities */ + case PIPE_CAP_DEPTH_BOUNDS_TEST: + return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS; /* nv4x capabilities */ case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_NPOT_TEXTURES: @@ -135,7 +140,6 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: case PIPE_CAP_START_INSTANCE: case PIPE_CAP_TEXTURE_MULTISAMPLE: - case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: @@ -162,6 +166,9 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: + case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: + case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: return 0; case PIPE_CAP_VENDOR_ID: @@ -313,12 +320,12 @@ nv30_screen_is_format_supported(struct pipe_screen *pscreen, unsigned bindings) { if (sample_count > 4) - return FALSE; + return false; if (!(0x00000017 & (1 << sample_count))) - return FALSE; + return false; if (!util_format_is_supported(format, bindings)) { - return FALSE; + return false; } /* transfers & shared are always supported */ @@ -656,6 +663,6 @@ nv30_screen_create(struct nouveau_device *dev) nouveau_pushbuf_kick(push, push->channel); - nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); + nouveau_fence_new(&screen->base, &screen->base.fence.current, false); return pscreen; } diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.h b/src/gallium/drivers/nouveau/nv30/nv30_screen.h index 3f2e47fec99..7b17b88097c 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.h +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.h @@ -40,7 +40,7 @@ struct nv30_screen { struct nouveau_heap *vp_data_heap; }; -static INLINE struct nv30_screen * +static inline struct nv30_screen * nv30_screen(struct pipe_screen *pscreen) { return (struct nv30_screen *)pscreen; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_state.c b/src/gallium/drivers/nouveau/nv30/nv30_state.c index 708ba34c1e5..fd604c2266d 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_state.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_state.c @@ -211,6 +211,7 @@ static void * nv30_zsa_state_create(struct pipe_context *pipe, const struct pipe_depth_stencil_alpha_state *cso) { + struct nouveau_object *eng3d = nv30_context(pipe)->screen->eng3d; struct nv30_zsa_stateobj *so; so = CALLOC_STRUCT(nv30_zsa_stateobj); @@ -223,6 +224,13 @@ nv30_zsa_state_create(struct pipe_context *pipe, SB_DATA (so, cso->depth.writemask); SB_DATA (so, cso->depth.enabled); + if (eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS) { + SB_MTHD35(so, DEPTH_BOUNDS_TEST_ENABLE, 3); + SB_DATA (so, cso->depth.bounds_test); + SB_DATA (so, fui(cso->depth.bounds_min)); + SB_DATA (so, fui(cso->depth.bounds_max)); + } + if (cso->stencil[0].enabled) { SB_MTHD30(so, STENCIL_ENABLE(0), 3); SB_DATA (so, 1); diff --git a/src/gallium/drivers/nouveau/nv30/nv30_state.h b/src/gallium/drivers/nouveau/nv30/nv30_state.h index e27e16fae82..ed3b8103a00 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_state.h +++ b/src/gallium/drivers/nouveau/nv30/nv30_state.h @@ -13,6 +13,8 @@ #define SB_DATA(so, u) (so)->data[(so)->size++] = (u) #define SB_MTHD30(so, mthd, size) \ SB_DATA((so), ((size) << 18) | (7 << 13) | NV30_3D_##mthd) +#define SB_MTHD35(so, mthd, size) \ + SB_DATA((so), ((size) << 18) | (7 << 13) | NV35_3D_##mthd) #define SB_MTHD40(so, mthd, size) \ SB_DATA((so), ((size) << 18) | (7 << 13) | NV40_3D_##mthd) @@ -30,7 +32,7 @@ struct nv30_rasterizer_stateobj { struct nv30_zsa_stateobj { struct pipe_depth_stencil_alpha_state pipe; - unsigned data[32]; + unsigned data[36]; unsigned size; }; @@ -80,7 +82,7 @@ struct nv30_vertprog { struct tgsi_shader_info info; struct draw_vertex_shader *draw; - boolean translated; + bool translated; unsigned enabled_ucps; uint16_t texcoord[10]; @@ -109,7 +111,7 @@ struct nv30_fragprog { struct tgsi_shader_info info; struct draw_fragment_shader *draw; - boolean translated; + bool translated; uint32_t *insn; unsigned insn_len; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c b/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c index a954dcce562..8957634f0fa 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c @@ -453,8 +453,8 @@ nv30_state_context_switch(struct nv30_context *nv30) nv30->base.pushbuf->user_priv = &nv30->bufctx; } -boolean -nv30_state_validate(struct nv30_context *nv30, uint32_t mask, boolean hwtnl) +bool +nv30_state_validate(struct nv30_context *nv30, uint32_t mask, bool hwtnl) { struct nouveau_screen *screen = &nv30->screen->base; struct nouveau_pushbuf *push = nv30->base.pushbuf; @@ -494,7 +494,7 @@ nv30_state_validate(struct nv30_context *nv30, uint32_t mask, boolean hwtnl) nouveau_pushbuf_bufctx(push, bctx); if (nouveau_pushbuf_validate(push)) { nouveau_pushbuf_bufctx(push, NULL); - return FALSE; + return false; } /*XXX*/ @@ -528,7 +528,7 @@ nv30_state_validate(struct nv30_context *nv30, uint32_t mask, boolean hwtnl) } } - return TRUE; + return true; } void diff --git a/src/gallium/drivers/nouveau/nv30/nv30_texture.c b/src/gallium/drivers/nouveau/nv30/nv30_texture.c index c3567217442..bfe21cceaa2 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_texture.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_texture.c @@ -37,7 +37,7 @@ #define NV40_WRAP(n) \ case PIPE_TEX_WRAP_##n: ret = NV40_3D_TEX_WRAP_S_##n; break -static INLINE unsigned +static inline unsigned wrap_mode(unsigned pipe) { unsigned ret = NV30_3D_TEX_WRAP_S_REPEAT; @@ -58,7 +58,7 @@ wrap_mode(unsigned pipe) return ret >> NV30_3D_TEX_WRAP_S__SHIFT; } -static INLINE unsigned +static inline unsigned filter_mode(const struct pipe_sampler_state *cso) { unsigned filter; @@ -104,7 +104,7 @@ filter_mode(const struct pipe_sampler_state *cso) return filter; } -static INLINE unsigned +static inline unsigned compare_mode(const struct pipe_sampler_state *cso) { if (cso->compare_mode != PIPE_TEX_COMPARE_R_TO_TEXTURE) @@ -201,7 +201,7 @@ nv30_bind_sampler_states(struct pipe_context *pipe, } } -static INLINE uint32_t +static inline uint32_t swizzle(const struct nv30_texfmt *fmt, unsigned cmp, unsigned swz) { uint32_t data = fmt->swz[swz].src << 8; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_transfer.c b/src/gallium/drivers/nouveau/nv30/nv30_transfer.c index 99bc0994ac2..214da6568c3 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_transfer.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_transfer.c @@ -41,33 +41,33 @@ * of different ways. */ -static INLINE boolean +static inline bool nv30_transfer_scaled(struct nv30_rect *src, struct nv30_rect *dst) { if (src->x1 - src->x0 != dst->x1 - dst->x0) - return TRUE; + return true; if (src->y1 - src->y0 != dst->y1 - dst->y0) - return TRUE; - return FALSE; + return true; + return false; } -static INLINE boolean +static inline bool nv30_transfer_blit(XFER_ARGS) { if (nv30->screen->eng3d->oclass < NV40_3D_CLASS) - return FALSE; + return false; if (dst->offset & 63 || dst->pitch & 63 || dst->d > 1) - return FALSE; + return false; if (dst->w < 2 || dst->h < 2) - return FALSE; + return false; if (dst->cpp > 4 || (dst->cpp == 1 && !dst->pitch)) - return FALSE; + return false; if (src->cpp > 4) - return FALSE; - return TRUE; + return false; + return true; } -static INLINE struct nouveau_heap * +static inline struct nouveau_heap * nv30_transfer_rect_vertprog(struct nv30_context *nv30) { struct nouveau_heap *heap = nv30->screen->vp_exec_heap; @@ -108,7 +108,7 @@ nv30_transfer_rect_vertprog(struct nv30_context *nv30) } -static INLINE struct nv04_resource * +static inline struct nv04_resource * nv30_transfer_rect_fragprog(struct nv30_context *nv30) { struct nv04_resource *fp = nv04_resource(nv30->blit_fp); @@ -368,29 +368,29 @@ nv30_transfer_rect_blit(XFER_ARGS) PUSH_DATA (push, NV30_3D_VERTEX_BEGIN_END_STOP); } -static boolean +static bool nv30_transfer_sifm(XFER_ARGS) { if (!src->pitch || (src->w | src->h) > 1024 || src->w < 2 || src->h < 2) - return FALSE; + return false; if (src->d > 1 || dst->d > 1) - return FALSE; + return false; if (dst->offset & 63) - return FALSE; + return false; if (!dst->pitch) { if ((dst->w | dst->h) > 2048 || dst->w < 2 || dst->h < 2) - return FALSE; + return false; } else { if (dst->domain != NOUVEAU_BO_VRAM) - return FALSE; + return false; if (dst->pitch & 63) - return FALSE; + return false; } - return TRUE; + return true; } static void @@ -481,14 +481,14 @@ nv30_transfer_rect_sifm(XFER_ARGS) * that name is still accurate on nv4x) error. */ -static boolean +static bool nv30_transfer_m2mf(XFER_ARGS) { if (!src->pitch || !dst->pitch) - return FALSE; + return false; if (nv30_transfer_scaled(src, dst)) - return FALSE; - return TRUE; + return false; + return true; } static void @@ -540,12 +540,12 @@ nv30_transfer_rect_m2mf(XFER_ARGS) } } -static boolean +static bool nv30_transfer_cpu(XFER_ARGS) { if (nv30_transfer_scaled(src, dst)) - return FALSE; - return TRUE; + return false; + return true; } static char * @@ -554,7 +554,7 @@ linear_ptr(struct nv30_rect *rect, char *base, int x, int y, int z) return base + (y * rect->pitch) + (x * rect->cpp); } -static INLINE unsigned +static inline unsigned swizzle2d(unsigned v, unsigned s) { v = (v | (v << 8)) & 0x00ff00ff; @@ -614,7 +614,7 @@ swizzle3d_ptr(struct nv30_rect *rect, char *base, int x, int y, int z) typedef char *(*get_ptr_t)(struct nv30_rect *, char *, int, int, int); -static INLINE get_ptr_t +static inline get_ptr_t get_ptr(struct nv30_rect *rect) { if (rect->pitch) @@ -653,7 +653,7 @@ nv30_transfer_rect(struct nv30_context *nv30, enum nv30_transfer_filter filter, { static const struct { char *name; - boolean (*possible)(XFER_ARGS); + bool (*possible)(XFER_ARGS); void (*execute)(XFER_ARGS); } *method, methods[] = { { "m2mf", nv30_transfer_m2mf, nv30_transfer_rect_m2mf }, diff --git a/src/gallium/drivers/nouveau/nv30/nv30_vbo.c b/src/gallium/drivers/nouveau/nv30/nv30_vbo.c index d4e384b21d2..8494549e9b1 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_vbo.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_vbo.c @@ -79,7 +79,7 @@ nv30_emit_vtxattr(struct nv30_context *nv30, struct pipe_vertex_buffer *vb, } } -static INLINE void +static inline void nv30_vbuf_range(struct nv30_context *nv30, int vbi, uint32_t *base, uint32_t *size) { @@ -119,7 +119,7 @@ nv30_prevalidate_vbufs(struct nv30_context *nv30) } else { nouveau_buffer_migrate(&nv30->base, buf, NOUVEAU_BO_GART); } - nv30->base.vbo_dirty = TRUE; + nv30->base.vbo_dirty = true; } } } @@ -160,10 +160,10 @@ nv30_update_user_vbufs(struct nv30_context *nv30) NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, NV30_3D_VTXBUF_DMA1); } - nv30->base.vbo_dirty = TRUE; + nv30->base.vbo_dirty = true; } -static INLINE void +static inline void nv30_release_user_vbufs(struct nv30_context *nv30) { uint32_t vbo_user = nv30->vbo_user; @@ -202,6 +202,9 @@ nv30_vbo_validate(struct nv30_context *nv30) return; redefine = MAX2(vertex->num_elements, nv30->state.num_vtxelts); + if (redefine == 0) + return; + BEGIN_NV04(push, NV30_3D(VTXFMT(0)), redefine); for (i = 0; i < vertex->num_elements; i++) { @@ -221,7 +224,7 @@ nv30_vbo_validate(struct nv30_context *nv30) for (i = 0; i < vertex->num_elements; i++) { struct nv04_resource *res; unsigned offset; - boolean user; + bool user; ve = &vertex->pipe[i]; vb = &nv30->vtxbuf[ve->vertex_buffer_index]; @@ -254,14 +257,12 @@ nv30_vertex_state_create(struct pipe_context *pipe, unsigned num_elements, struct translate_key transkey; unsigned i; - assert(num_elements); - so = MALLOC(sizeof(*so) + sizeof(*so->element) * num_elements); if (!so) return NULL; memcpy(so->pipe, elements, sizeof(*elements) * num_elements); so->num_elements = num_elements; - so->need_conversion = FALSE; + so->need_conversion = false; transkey.nr_elements = 0; transkey.output_stride = 0; @@ -284,7 +285,7 @@ nv30_vertex_state_create(struct pipe_context *pipe, unsigned num_elements, return NULL; } so->element[i].state = nv30_vtxfmt(pipe->screen, fmt)->hw; - so->need_conversion = TRUE; + so->need_conversion = true; } if (1) { @@ -452,7 +453,7 @@ nv30_draw_elements_inline_u32_short(struct nouveau_pushbuf *push, } static void -nv30_draw_elements(struct nv30_context *nv30, boolean shorten, +nv30_draw_elements(struct nv30_context *nv30, bool shorten, unsigned mode, unsigned start, unsigned count, unsigned instance_count, int32_t index_bias) { @@ -461,13 +462,11 @@ nv30_draw_elements(struct nv30_context *nv30, boolean shorten, struct nouveau_object *eng3d = nv30->screen->eng3d; unsigned prim = nv30_prim_gl(mode); -#if 0 /*XXX*/ - if (index_bias != nv30->state.index_bias) { - BEGIN_NV04(push, NV30_3D(VB_ELEMENT_BASE), 1); + if (eng3d->oclass >= NV40_3D_CLASS && index_bias != nv30->state.index_bias) { + BEGIN_NV04(push, NV40_3D(VB_ELEMENT_BASE), 1); PUSH_DATA (push, index_bias); nv30->state.index_bias = index_bias; } -#endif if (eng3d->oclass == NV40_3D_CLASS && index_size > 1 && nv30->idxbuf.buffer) { @@ -564,7 +563,7 @@ nv30_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) if (nv30->vbo_user && !(nv30->dirty & (NV30_NEW_VERTEX | NV30_NEW_ARRAYS))) nv30_update_user_vbufs(nv30); - nv30_state_validate(nv30, ~0, TRUE); + nv30_state_validate(nv30, ~0, true); if (nv30->draw_flags) { nv30_render_vbo(pipe, info); return; @@ -578,17 +577,17 @@ nv30_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) if (!nv30->vtxbuf[i].buffer) continue; if (nv30->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) - nv30->base.vbo_dirty = TRUE; + nv30->base.vbo_dirty = true; } if (!nv30->base.vbo_dirty && nv30->idxbuf.buffer && nv30->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) - nv30->base.vbo_dirty = TRUE; + nv30->base.vbo_dirty = true; if (nv30->base.vbo_dirty) { BEGIN_NV04(push, NV30_3D(VTX_CACHE_INVALIDATE_1710), 1); PUSH_DATA (push, 0); - nv30->base.vbo_dirty = FALSE; + nv30->base.vbo_dirty = false; } if (!info->indexed) { @@ -596,7 +595,7 @@ nv30_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) info->mode, info->start, info->count, info->instance_count); } else { - boolean shorten = info->max_index <= 65535; + bool shorten = info->max_index <= 65535; if (info->primitive_restart != nv30->state.prim_restart) { if (info->primitive_restart) { @@ -605,7 +604,7 @@ nv30_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) PUSH_DATA (push, info->restart_index); if (info->restart_index > 65535) - shorten = FALSE; + shorten = false; } else { BEGIN_NV04(push, NV40_3D(PRIM_RESTART_ENABLE), 1); PUSH_DATA (push, 0); @@ -617,7 +616,7 @@ nv30_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) PUSH_DATA (push, info->restart_index); if (info->restart_index > 65535) - shorten = FALSE; + shorten = false; } nv30_draw_elements(nv30, shorten, diff --git a/src/gallium/drivers/nouveau/nv30/nv30_vertprog.c b/src/gallium/drivers/nouveau/nv30/nv30_vertprog.c index 4d4145d10b5..ee0a6280d7a 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_vertprog.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_vertprog.c @@ -48,7 +48,7 @@ nv30_vertprog_destroy(struct nv30_vertprog *vp) vp->consts = NULL; vp->nr_consts = 0; - vp->translated = FALSE; + vp->translated = false; } void @@ -58,8 +58,8 @@ nv30_vertprog_validate(struct nv30_context *nv30) struct nouveau_object *eng3d = nv30->screen->eng3d; struct nv30_vertprog *vp = nv30->vertprog.program; struct nv30_fragprog *fp = nv30->fragprog.program; - boolean upload_code = FALSE; - boolean upload_data = FALSE; + bool upload_code = false; + bool upload_data = false; unsigned i; if (nv30->dirty & NV30_NEW_FRAGPROG) { @@ -125,7 +125,7 @@ nv30_vertprog_validate(struct nv30_context *nv30) } } - upload_code = TRUE; + upload_code = true; } if (vp->nr_consts && !vp->data) { @@ -166,8 +166,8 @@ nv30_vertprog_validate(struct nv30_context *nv30) } } - upload_code = TRUE; - upload_data = TRUE; + upload_code = true; + upload_data = true; } if (vp->nr_consts) { diff --git a/src/gallium/drivers/nouveau/nv30/nv30_winsys.h b/src/gallium/drivers/nouveau/nv30/nv30_winsys.h index 5cee5df60ce..2324b517c44 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_winsys.h +++ b/src/gallium/drivers/nouveau/nv30/nv30_winsys.h @@ -19,34 +19,34 @@ #define NV40_3D_PRIM_RESTART_ENABLE 0x1dac #define NV40_3D_PRIM_RESTART_INDEX 0x1db0 -static INLINE void +static inline void PUSH_RELOC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t offset, uint32_t flags, uint32_t vor, uint32_t tor) { nouveau_pushbuf_reloc(push, bo, offset, flags, vor, tor); } -static INLINE struct nouveau_bufctx * +static inline struct nouveau_bufctx * bufctx(struct nouveau_pushbuf *push) { struct nouveau_bufctx **pctx = push->user_priv; return *pctx; } -static INLINE void +static inline void PUSH_RESET(struct nouveau_pushbuf *push, int bin) { nouveau_bufctx_reset(bufctx(push), bin); } -static INLINE void +static inline void PUSH_REFN(struct nouveau_pushbuf *push, int bin, struct nouveau_bo *bo, uint32_t access) { nouveau_bufctx_refn(bufctx(push), bin, bo, access); } -static INLINE void +static inline void PUSH_MTHDl(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nouveau_bo *bo, uint32_t offset, uint32_t access) { @@ -55,7 +55,7 @@ PUSH_MTHDl(struct nouveau_pushbuf *push, int subc, int mthd, int bin, PUSH_DATA(push, bo->offset + offset); } -static INLINE void +static inline void PUSH_MTHDo(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nouveau_bo *bo, uint32_t access, uint32_t vor, uint32_t tor) { @@ -67,7 +67,7 @@ PUSH_MTHDo(struct nouveau_pushbuf *push, int subc, int mthd, int bin, PUSH_DATA(push, tor); } -static INLINE void +static inline void PUSH_MTHDs(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nouveau_bo *bo, uint32_t data, uint32_t access, uint32_t vor, uint32_t tor) @@ -80,7 +80,7 @@ PUSH_MTHDs(struct nouveau_pushbuf *push, int subc, int mthd, int bin, PUSH_DATA(push, data | tor); } -static INLINE struct nouveau_bufref * +static inline struct nouveau_bufref * PUSH_MTHD(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nouveau_bo *bo, uint32_t data, uint32_t access, uint32_t vor, uint32_t tor) @@ -99,7 +99,7 @@ PUSH_MTHD(struct nouveau_pushbuf *push, int subc, int mthd, int bin, return bref; } -static INLINE void +static inline void PUSH_RESRC(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nv04_resource *r, uint32_t data, uint32_t access, uint32_t vor, uint32_t tor) @@ -108,14 +108,14 @@ PUSH_RESRC(struct nouveau_pushbuf *push, int subc, int mthd, int bin, r->domain | access, vor, tor)->priv = r; } -static INLINE void +static inline void BEGIN_NV04(struct nouveau_pushbuf *push, int subc, int mthd, int size) { PUSH_SPACE(push, size + 1); PUSH_DATA (push, 0x00000000 | (size << 18) | (subc << 13) | mthd); } -static INLINE void +static inline void BEGIN_NI04(struct nouveau_pushbuf *push, int subc, int mthd, int size) { PUSH_SPACE(push, size + 1); diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c index 9ef16965f39..e68d23e5587 100644 --- a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c +++ b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c @@ -44,7 +44,7 @@ struct nvfx_fpc { struct util_dynarray label_relocs; }; -static INLINE struct nvfx_reg +static inline struct nvfx_reg temp(struct nvfx_fpc *fpc) { int idx = __builtin_ctzll(~fpc->r_temps); @@ -60,7 +60,7 @@ temp(struct nvfx_fpc *fpc) return nvfx_reg(NVFXSR_TEMP, idx); } -static INLINE void +static inline void release_temps(struct nvfx_fpc *fpc) { fpc->r_temps &= ~fpc->r_temps_discard; @@ -373,7 +373,7 @@ nv40_fp_brk(struct nvfx_fpc *fpc) hw[3] = 0; } -static INLINE struct nvfx_src +static inline struct nvfx_src tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc) { struct nvfx_src src; @@ -415,7 +415,7 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc) return src; } -static INLINE struct nvfx_reg +static inline struct nvfx_reg tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) { switch (fdst->Register.File) { case TGSI_FILE_OUTPUT: @@ -430,7 +430,7 @@ tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) { } } -static INLINE int +static inline int tgsi_mask(uint tgsi) { int mask = 0; @@ -442,7 +442,7 @@ tgsi_mask(uint tgsi) return mask; } -static boolean +static bool nvfx_fragprog_parse_instruction(struct nvfx_fpc *fpc, const struct tgsi_full_instruction *finst) { @@ -455,7 +455,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_fpc *fpc, int i; if (finst->Instruction.Opcode == TGSI_OPCODE_END) - return TRUE; + return true; for (i = 0; i < finst->Instruction.NumSrcRegs; i++) { const struct tgsi_full_src_register *fsrc; @@ -525,7 +525,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_fpc *fpc, break; default: NOUVEAU_ERR("bad src file\n"); - return FALSE; + return false; } } @@ -868,12 +868,12 @@ nvfx_fragprog_parse_instruction(struct nvfx_fpc *fpc, default: NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode); - return FALSE; + return false; } out: release_temps(fpc); - return TRUE; + return true; nv3x_cflow: { static int warned = 0; @@ -887,7 +887,7 @@ nv3x_cflow: goto out; } -static boolean +static bool nvfx_fragprog_parse_decl_input(struct nvfx_fpc *fpc, const struct tgsi_full_declaration *fdec) { @@ -917,17 +917,17 @@ nvfx_fragprog_parse_decl_input(struct nvfx_fpc *fpc, case TGSI_SEMANTIC_GENERIC: case TGSI_SEMANTIC_PCOORD: /* will be assigned to remaining TC slots later */ - return TRUE; + return true; default: assert(0); - return FALSE; + return false; } fpc->r_input[idx] = nvfx_reg(NVFXSR_INPUT, hw); - return TRUE; + return true; } -static boolean +static bool nvfx_fragprog_assign_generic(struct nvfx_fpc *fpc, const struct tgsi_full_declaration *fdec) { @@ -954,16 +954,16 @@ nvfx_fragprog_assign_generic(struct nvfx_fpc *fpc, } hw = NVFX_FP_OP_INPUT_SRC_TC(hw); fpc->r_input[idx] = nvfx_reg(NVFXSR_INPUT, hw); - return TRUE; + return true; } } - return FALSE; + return false; default: - return TRUE; + return true; } } -static boolean +static bool nvfx_fragprog_parse_decl_output(struct nvfx_fpc *fpc, const struct tgsi_full_declaration *fdec) { @@ -984,20 +984,20 @@ nvfx_fragprog_parse_decl_output(struct nvfx_fpc *fpc, } if(hw > ((fpc->is_nv4x) ? 4 : 2)) { NOUVEAU_ERR("bad rcol index\n"); - return FALSE; + return false; } break; default: NOUVEAU_ERR("bad output semantic\n"); - return FALSE; + return false; } fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw); fpc->r_temps |= (1ULL << hw); - return TRUE; + return true; } -static boolean +static bool nvfx_fragprog_prepare(struct nvfx_fpc *fpc) { struct tgsi_parse_context p; @@ -1081,17 +1081,17 @@ nvfx_fragprog_prepare(struct nvfx_fpc *fpc) fpc->r_temps_discard = 0ULL; } - return TRUE; + return true; out_err: FREE(fpc->r_temp); fpc->r_temp = NULL; tgsi_parse_free(&p); - return FALSE; + return false; } -DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE) +DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", false) void _nvfx_fragprog_translate(uint16_t oclass, struct nv30_fragprog *fp) @@ -1100,7 +1100,7 @@ _nvfx_fragprog_translate(uint16_t oclass, struct nv30_fragprog *fp) struct nvfx_fpc *fpc = NULL; struct util_dynarray insns; - fp->translated = FALSE; + fp->translated = false; fp->point_sprite_control = 0; fp->vp_or = 0; @@ -1182,7 +1182,7 @@ _nvfx_fragprog_translate(uint16_t oclass, struct nv30_fragprog *fp) debug_printf("\n"); } - fp->translated = TRUE; + fp->translated = true; out: tgsi_parse_free(&parse); diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_shader.h b/src/gallium/drivers/nouveau/nv30/nvfx_shader.h index 9538a793d7e..e66d8af7620 100644 --- a/src/gallium/drivers/nouveau/nv30/nvfx_shader.h +++ b/src/gallium/drivers/nouveau/nv30/nvfx_shader.h @@ -448,8 +448,8 @@ struct nvfx_insn struct nvfx_src src[3]; }; -static INLINE struct nvfx_insn -nvfx_insn(boolean sat, unsigned op, int unit, struct nvfx_reg dst, unsigned mask, struct nvfx_src s0, struct nvfx_src s1, struct nvfx_src s2) +static inline struct nvfx_insn +nvfx_insn(bool sat, unsigned op, int unit, struct nvfx_reg dst, unsigned mask, struct nvfx_src s0, struct nvfx_src s1, struct nvfx_src s2) { struct nvfx_insn insn = { .op = op, @@ -468,7 +468,7 @@ nvfx_insn(boolean sat, unsigned op, int unit, struct nvfx_reg dst, unsigned mask return insn; } -static INLINE struct nvfx_reg +static inline struct nvfx_reg nvfx_reg(int type, int index) { struct nvfx_reg temp = { @@ -478,7 +478,7 @@ nvfx_reg(int type, int index) return temp; } -static INLINE struct nvfx_src +static inline struct nvfx_src nvfx_src(struct nvfx_reg reg) { struct nvfx_src temp = { @@ -491,7 +491,7 @@ nvfx_src(struct nvfx_reg reg) return temp; } -static INLINE struct nvfx_src +static inline struct nvfx_src nvfx_src_swz(struct nvfx_src src, int x, int y, int z, int w) { struct nvfx_src dst = src; @@ -503,14 +503,14 @@ nvfx_src_swz(struct nvfx_src src, int x, int y, int z, int w) return dst; } -static INLINE struct nvfx_src +static inline struct nvfx_src nvfx_src_neg(struct nvfx_src src) { src.negate = !src.negate; return src; } -static INLINE struct nvfx_src +static inline struct nvfx_src nvfx_src_abs(struct nvfx_src src) { src.abs = 1; @@ -529,7 +529,7 @@ struct nv30_vertprog; void _nvfx_fragprog_translate(uint16_t oclass, struct nv30_fragprog *fp); -boolean +bool _nvfx_vertprog_translate(uint16_t oclass, struct nv30_vertprog *vp); #endif diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c b/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c index 1ce0589be71..5757eb1fb16 100644 --- a/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c +++ b/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c @@ -416,7 +416,7 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) { return src; } -static INLINE struct nvfx_reg +static inline struct nvfx_reg tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) { struct nvfx_reg dst; @@ -455,7 +455,7 @@ tgsi_mask(uint tgsi) return mask; } -static boolean +static bool nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc, unsigned idx, const struct tgsi_full_instruction *finst) { @@ -466,7 +466,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc, struct nvfx_insn insn; struct nvfx_relocation reloc; struct nvfx_loop_entry loop; - boolean sat = FALSE; + bool sat = false; int mask; int ai = -1, ci = -1, ii = -1; int i; @@ -524,25 +524,25 @@ nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc, break; default: NOUVEAU_ERR("bad src file\n"); - return FALSE; + return false; } } for (i = 0; i < finst->Instruction.NumSrcRegs; i++) { if(src[i].reg.type < 0) - return FALSE; + return false; } if(finst->Dst[0].Register.File == TGSI_FILE_ADDRESS && finst->Instruction.Opcode != TGSI_OPCODE_ARL) - return FALSE; + return false; final_dst = dst = tgsi_dst(vpc, &finst->Dst[0]); mask = tgsi_mask(finst->Dst[0].Register.WriteMask); if(finst->Instruction.Saturate) { assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL); if (vpc->is_nv4x) - sat = TRUE; + sat = true; else if(dst.type != NVFXSR_TEMP) dst = temp(vpc); @@ -793,7 +793,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc, break; default: NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode); - return FALSE; + return false; } if(finst->Instruction.Saturate && !vpc->is_nv4x) { @@ -804,10 +804,10 @@ nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc, } release_temps(vpc); - return TRUE; + return true; } -static boolean +static bool nvfx_vertprog_parse_decl_output(struct nvfx_vpc *vpc, const struct tgsi_full_declaration *fdec) { @@ -825,7 +825,7 @@ nvfx_vertprog_parse_decl_output(struct nvfx_vpc *vpc, vpc->r_result[idx] = temp(vpc); vpc->r_temps_discard = 0; vpc->cvtx_idx = idx; - return TRUE; + return true; case TGSI_SEMANTIC_COLOR: if (fdec->Semantic.Index == 0) { hw = NVFX_VP(INST_DEST_COL0); @@ -834,7 +834,7 @@ nvfx_vertprog_parse_decl_output(struct nvfx_vpc *vpc, hw = NVFX_VP(INST_DEST_COL1); } else { NOUVEAU_ERR("bad colour semantic index\n"); - return FALSE; + return false; } break; case TGSI_SEMANTIC_BCOLOR: @@ -845,7 +845,7 @@ nvfx_vertprog_parse_decl_output(struct nvfx_vpc *vpc, hw = NVFX_VP(INST_DEST_BFC1); } else { NOUVEAU_ERR("bad bcolour semantic index\n"); - return FALSE; + return false; } break; case TGSI_SEMANTIC_FOG: @@ -868,22 +868,22 @@ nvfx_vertprog_parse_decl_output(struct nvfx_vpc *vpc, if (i == num_texcoords) { vpc->r_result[idx] = nvfx_reg(NVFXSR_NONE, 0); - return TRUE; + return true; } break; case TGSI_SEMANTIC_EDGEFLAG: vpc->r_result[idx] = nvfx_reg(NVFXSR_NONE, 0); - return TRUE; + return true; default: NOUVEAU_ERR("bad output semantic\n"); - return FALSE; + return false; } vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw); - return TRUE; + return true; } -static boolean +static bool nvfx_vertprog_prepare(struct nvfx_vpc *vpc) { struct tgsi_parse_context p; @@ -924,7 +924,7 @@ nvfx_vertprog_prepare(struct nvfx_vpc *vpc) break; case TGSI_FILE_OUTPUT: if (!nvfx_vertprog_parse_decl_output(vpc, fdec)) - return FALSE; + return false; break; default: break; @@ -961,12 +961,12 @@ nvfx_vertprog_prepare(struct nvfx_vpc *vpc) } vpc->r_temps_discard = 0; - return TRUE; + return true; } -DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", FALSE) +DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", false) -boolean +bool _nvfx_vertprog_translate(uint16_t oclass, struct nv30_vertprog *vp) { struct tgsi_parse_context parse; @@ -975,13 +975,13 @@ _nvfx_vertprog_translate(uint16_t oclass, struct nv30_vertprog *vp) struct util_dynarray insns; int i, ucps; - vp->translated = FALSE; + vp->translated = false; vp->nr_insns = 0; vp->nr_consts = 0; vpc = CALLOC_STRUCT(nvfx_vpc); if (!vpc) - return FALSE; + return false; vpc->is_nv4x = (oclass >= NV40_3D_CLASS) ? ~0 : 0; vpc->vp = vp; vpc->pipe = vp->pipe; @@ -990,7 +990,7 @@ _nvfx_vertprog_translate(uint16_t oclass, struct nv30_vertprog *vp) if (!nvfx_vertprog_prepare(vpc)) { FREE(vpc); - return FALSE; + return false; } /* Redirect post-transform vertex position to a temp if user clip @@ -1108,7 +1108,7 @@ _nvfx_vertprog_translate(uint16_t oclass, struct nv30_vertprog *vp) debug_printf("\n"); } - vp->translated = TRUE; + vp->translated = true; out: tgsi_parse_free(&parse); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_blit.h b/src/gallium/drivers/nouveau/nv50/nv50_blit.h index 756c4c11bf6..0ccec568d3a 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_blit.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_blit.h @@ -37,7 +37,7 @@ nv50_resource_resolve(struct pipe_context *, const struct pipe_resolve_info *); #define NV50_BLIT_TEXTURE_2D_ARRAY 5 #define NV50_BLIT_MAX_TEXTURE_TYPES 6 -static INLINE unsigned +static inline unsigned nv50_blit_texture_type(enum pipe_texture_target target) { switch (target) { @@ -52,7 +52,7 @@ nv50_blit_texture_type(enum pipe_texture_target target) } } -static INLINE unsigned +static inline unsigned nv50_blit_get_tgsi_texture_target(enum pipe_texture_target target) { switch (target) { @@ -67,7 +67,7 @@ nv50_blit_get_tgsi_texture_target(enum pipe_texture_target target) } } -static INLINE enum pipe_texture_target +static inline enum pipe_texture_target nv50_blit_reinterpret_pipe_texture_target(enum pipe_texture_target target) { switch (target) { @@ -81,7 +81,7 @@ nv50_blit_reinterpret_pipe_texture_target(enum pipe_texture_target target) } } -static INLINE unsigned +static inline unsigned nv50_blit_get_filter(const struct pipe_blit_info *info) { if (info->dst.resource->nr_samples < info->src.resource->nr_samples) @@ -102,7 +102,7 @@ nv50_blit_get_filter(const struct pipe_blit_info *info) /* Since shaders cannot export stencil, we cannot copy stencil values when * rendering to ZETA, so we attach the ZS surface to a colour render target. */ -static INLINE enum pipe_format +static inline enum pipe_format nv50_blit_zeta_to_colour_format(enum pipe_format format) { switch (format) { @@ -127,7 +127,7 @@ nv50_blit_zeta_to_colour_format(enum pipe_format format) } -static INLINE uint16_t +static inline uint16_t nv50_blit_derive_color_mask(const struct pipe_blit_info *info) { const unsigned mask = info->mask; @@ -162,7 +162,7 @@ nv50_blit_derive_color_mask(const struct pipe_blit_info *info) return color_mask; } -static INLINE uint32_t +static inline uint32_t nv50_blit_eng2d_get_mask(const struct pipe_blit_info *info) { uint32_t mask = 0; @@ -191,8 +191,8 @@ nv50_blit_eng2d_get_mask(const struct pipe_blit_info *info) # define nv50_format_table nvc0_format_table #endif -/* return TRUE for formats that can be converted among each other by NVC0_2D */ -static INLINE boolean +/* return true for formats that can be converted among each other by NVC0_2D */ +static inline bool nv50_2d_dst_format_faithful(enum pipe_format format) { const uint64_t mask = @@ -201,7 +201,7 @@ nv50_2d_dst_format_faithful(enum pipe_format format) uint8_t id = nv50_format_table[format].rt; return (id >= 0xc0) && (mask & (1ULL << (id - 0xc0))); } -static INLINE boolean +static inline bool nv50_2d_src_format_faithful(enum pipe_format format) { const uint64_t mask = @@ -211,7 +211,7 @@ nv50_2d_src_format_faithful(enum pipe_format format) return (id >= 0xc0) && (mask & (1ULL << (id - 0xc0))); } -static INLINE boolean +static inline bool nv50_2d_format_supported(enum pipe_format format) { uint8_t id = nv50_format_table[format].rt; @@ -219,7 +219,7 @@ nv50_2d_format_supported(enum pipe_format format) (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))); } -static INLINE boolean +static inline bool nv50_2d_dst_format_ops_supported(enum pipe_format format) { uint8_t id = nv50_format_table[format].rt; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.c b/src/gallium/drivers/nouveau/nv50/nv50_context.c index 5b5d3912c20..f8d46db7c67 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_context.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_context.c @@ -64,12 +64,12 @@ nv50_memory_barrier(struct pipe_context *pipe, unsigned flags) if (!nv50->vtxbuf[i].buffer) continue; if (nv50->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) - nv50->base.vbo_dirty = TRUE; + nv50->base.vbo_dirty = true; } if (nv50->idxbuf.buffer && nv50->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) - nv50->base.vbo_dirty = TRUE; + nv50->base.vbo_dirty = true; for (s = 0; s < 3 && !nv50->cb_dirty; ++s) { uint32_t valid = nv50->constbuf_valid[s]; @@ -87,7 +87,7 @@ nv50_memory_barrier(struct pipe_context *pipe, unsigned flags) continue; if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) - nv50->cb_dirty = TRUE; + nv50->cb_dirty = true; } } } @@ -100,9 +100,9 @@ nv50_default_kick_notify(struct nouveau_pushbuf *push) if (screen) { nouveau_fence_next(&screen->base); - nouveau_fence_update(&screen->base, TRUE); + nouveau_fence_update(&screen->base, true); if (screen->cur_ctx) - screen->cur_ctx->state.flushed = TRUE; + screen->cur_ctx->state.flushed = true; } } @@ -310,7 +310,7 @@ nv50_create(struct pipe_screen *pscreen, void *priv) nv50->base.invalidate_resource_storage = nv50_invalidate_resource_storage; if (screen->base.device->chipset < 0x84 || - debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) { + debug_get_bool_option("NOUVEAU_PMPEG", false)) { /* PMPEG */ nouveau_context_init_vdec(&nv50->base); } else if (screen->base.device->chipset < 0x98 || @@ -351,7 +351,7 @@ out_err: } void -nv50_bufctx_fence(struct nouveau_bufctx *bufctx, boolean on_flush) +nv50_bufctx_fence(struct nouveau_bufctx *bufctx, bool on_flush) { struct nouveau_list *list = on_flush ? &bufctx->current : &bufctx->pending; struct nouveau_list *it; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.h b/src/gallium/drivers/nouveau/nv50/nv50_context.h index 1f123ef7e92..ce12e714774 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_context.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_context.h @@ -91,7 +91,7 @@ struct nv50_blitctx; -boolean nv50_blitctx_create(struct nv50_context *); +bool nv50_blitctx_create(struct nv50_context *); struct nv50_context { struct nouveau_context base; @@ -102,7 +102,7 @@ struct nv50_context { struct nouveau_bufctx *bufctx; uint32_t dirty; - boolean cb_dirty; + bool cb_dirty; struct nv50_graph_state state; @@ -152,26 +152,26 @@ struct nv50_context { unsigned sample_mask; unsigned min_samples; - boolean vbo_push_hint; + bool vbo_push_hint; uint32_t rt_array_mode; struct pipe_query *cond_query; - boolean cond_cond; /* inverted rendering condition */ + bool cond_cond; /* inverted rendering condition */ uint cond_mode; uint32_t cond_condmode; /* the calculated condition */ struct nv50_blitctx *blit; }; -static INLINE struct nv50_context * +static inline struct nv50_context * nv50_context(struct pipe_context *pipe) { return (struct nv50_context *)pipe; } /* return index used in nv50_context arrays for a specific shader type */ -static INLINE unsigned +static inline unsigned nv50_context_shader_stage(unsigned pipe) { switch (pipe) { @@ -188,7 +188,7 @@ nv50_context_shader_stage(unsigned pipe) /* nv50_context.c */ struct pipe_context *nv50_create(struct pipe_screen *, void *); -void nv50_bufctx_fence(struct nouveau_bufctx *, boolean on_flush); +void nv50_bufctx_fence(struct nouveau_bufctx *, bool on_flush); void nv50_default_kick_notify(struct nouveau_pushbuf *); @@ -202,7 +202,7 @@ void nv50_query_pushbuf_submit(struct nouveau_pushbuf *, void nv84_query_fifo_wait(struct nouveau_pushbuf *, struct pipe_query *); void nva0_so_target_save_offset(struct pipe_context *, struct pipe_stream_output_target *, - unsigned index, boolean seralize); + unsigned index, bool seralize); #define NVA0_QUERY_STREAM_OUTPUT_BUFFER_OFFSET (PIPE_QUERY_TYPES + 0) @@ -221,8 +221,8 @@ extern void nv50_init_state_functions(struct nv50_context *); /* nv50_state_validate.c */ /* @words: check for space before emitting relocs */ -extern boolean nv50_state_validate(struct nv50_context *, uint32_t state_mask, - unsigned space_words); +extern bool nv50_state_validate(struct nv50_context *, uint32_t state_mask, + unsigned space_words); /* nv50_surface.c */ extern void nv50_clear(struct pipe_context *, unsigned buffers, diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c index 0f86ba1de0d..49a93bf1d91 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c @@ -44,7 +44,7 @@ */ #define U_V PIPE_BIND_VERTEX_BUFFER #define U_T PIPE_BIND_SAMPLER_VIEW -#define U_I PIPE_BIND_SHADER_RESOURCE | PIPE_BIND_COMPUTE_RESOURCE +#define U_I PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE | PIPE_BIND_COMPUTE_RESOURCE #define U_TR PIPE_BIND_RENDER_TARGET | U_T #define U_IR U_TR | U_I #define U_TB PIPE_BIND_BLENDABLE | U_TR diff --git a/src/gallium/drivers/nouveau/nv50/nv50_miptree.c b/src/gallium/drivers/nouveau/nv50/nv50_miptree.c index f15d8f3ecb6..92d49e49ff2 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_miptree.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_miptree.c @@ -30,7 +30,7 @@ uint32_t nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz, - boolean is_3d) + bool is_3d) { uint32_t tile_mode = 0x000; @@ -59,13 +59,13 @@ nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz, } static uint32_t -nv50_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz, boolean is_3d) +nv50_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz, bool is_3d) { return nv50_tex_choose_tile_dims_helper(nx, ny * 2, nz, is_3d); } static uint32_t -nv50_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) +nv50_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed) { const unsigned ms = util_logbase2(mt->base.base.nr_samples); uint32_t tile_flags; @@ -184,7 +184,7 @@ nv50_miptree_get_handle(struct pipe_screen *pscreen, unsigned stride; if (!mt || !mt->base.bo) - return FALSE; + return false; stride = mt->level[0].pitch; @@ -204,7 +204,7 @@ const struct u_resource_vtbl nv50_miptree_vtbl = u_default_transfer_inline_write /* transfer_inline_write */ }; -static INLINE boolean +static inline bool nv50_miptree_init_ms_mode(struct nv50_miptree *mt) { switch (mt->base.base.nr_samples) { @@ -228,12 +228,12 @@ nv50_miptree_init_ms_mode(struct nv50_miptree *mt) break; default: NOUVEAU_ERR("invalid nr_samples: %u\n", mt->base.base.nr_samples); - return FALSE; + return false; } - return TRUE; + return true; } -boolean +bool nv50_miptree_init_layout_linear(struct nv50_miptree *mt, unsigned pitch_align) { struct pipe_resource *pt = &mt->base.base; @@ -241,12 +241,12 @@ nv50_miptree_init_layout_linear(struct nv50_miptree *mt, unsigned pitch_align) unsigned h = pt->height0; if (util_format_is_depth_or_stencil(pt->format)) - return FALSE; + return false; if ((pt->last_level > 0) || (pt->depth0 > 1) || (pt->array_size > 1)) - return FALSE; + return false; if (mt->ms_x | mt->ms_y) - return FALSE; + return false; mt->level[0].pitch = align(pt->width0 * blocksize, pitch_align); @@ -256,7 +256,7 @@ nv50_miptree_init_layout_linear(struct nv50_miptree *mt, unsigned pitch_align) mt->total_size = mt->level[0].pitch * h; - return TRUE; + return true; } static void @@ -335,7 +335,7 @@ nv50_miptree_create(struct pipe_screen *pscreen, struct nouveau_device *dev = nouveau_screen(pscreen)->device; struct nv50_miptree *mt = CALLOC_STRUCT(nv50_miptree); struct pipe_resource *pt = &mt->base.base; - boolean compressed = dev->drm_version >= 0x01000101; + bool compressed = dev->drm_version >= 0x01000101; int ret; union nouveau_bo_config bo_config; uint32_t bo_flags; @@ -438,7 +438,7 @@ nv50_miptree_from_handle(struct pipe_screen *pscreen, /* Offset of zslice @z from start of level @l. */ -INLINE unsigned +inline unsigned nv50_mt_zslice_offset(const struct nv50_miptree *mt, unsigned l, unsigned z) { const struct pipe_resource *pt = &mt->base.base; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c b/src/gallium/drivers/nouveau/nv50/nv50_program.c index aaca4c550d9..02dc3677259 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_program.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c @@ -25,7 +25,7 @@ #include "codegen/nv50_ir_driver.h" -static INLINE unsigned +static inline unsigned bitcount4(const uint32_t val) { static const uint8_t cnt[16] @@ -104,7 +104,7 @@ nv50_vertprog_assign_slots(struct nv50_ir_prog_info *info) prog->vp.bfc[info->out[i].si] = i; break; case TGSI_SEMANTIC_LAYER: - prog->gp.has_layer = TRUE; + prog->gp.has_layer = true; prog->gp.layerid = n; break; case TGSI_SEMANTIC_VIEWPORT_INDEX: @@ -316,7 +316,7 @@ nv50_program_create_strmout_state(const struct nv50_ir_prog_info *info, return so; } -boolean +bool nv50_program_translate(struct nv50_program *prog, uint16_t chipset) { struct nv50_ir_prog_info *info; @@ -325,7 +325,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t chipset) info = CALLOC_STRUCT(nv50_ir_prog_info); if (!info) - return FALSE; + return false; info->type = prog->type; info->target = chipset; @@ -410,7 +410,7 @@ out: return !ret; } -boolean +bool nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog) { struct nouveau_heap *heap; @@ -423,7 +423,7 @@ nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog) case PIPE_SHADER_FRAGMENT: heap = nv50->screen->gp_code_heap; break; default: assert(!"invalid program type"); - return FALSE; + return false; } ret = nouveau_heap_alloc(heap, size, prog, &prog->mem); @@ -440,7 +440,7 @@ nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog) ret = nouveau_heap_alloc(heap, size, prog, &prog->mem); if (ret) { NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size); - return FALSE; + return false; } } prog->code_base = prog->mem->start; @@ -448,10 +448,10 @@ nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog) ret = nv50_tls_realloc(nv50->screen, prog->tls_space); if (ret < 0) { nouveau_heap_free(&prog->mem); - return FALSE; + return false; } if (ret > 0) - nv50->state.new_tls_space = TRUE; + nv50->state.new_tls_space = true; if (prog->fixups) nv50_ir_relocate_code(prog->fixups, prog->code, prog->code_base, 0, 0); @@ -463,7 +463,7 @@ nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog) BEGIN_NV04(nv50->base.pushbuf, NV50_3D(CODE_CB_FLUSH), 1); PUSH_DATA (nv50->base.pushbuf, 0); - return TRUE; + return true; } void diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.h b/src/gallium/drivers/nouveau/nv50/nv50_program.h index fe6bd6025be..5d3ff5644d2 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_program.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_program.h @@ -53,7 +53,7 @@ struct nv50_program { struct pipe_shader_state pipe; ubyte type; - boolean translated; + bool translated; uint32_t *code; unsigned code_size; @@ -104,8 +104,8 @@ struct nv50_program { struct nv50_stream_output_state *so; }; -boolean nv50_program_translate(struct nv50_program *, uint16_t chipset); -boolean nv50_program_upload_code(struct nv50_context *, struct nv50_program *); +bool nv50_program_translate(struct nv50_program *, uint16_t chipset); +bool nv50_program_upload_code(struct nv50_context *, struct nv50_program *); void nv50_program_destroy(struct nv50_context *, struct nv50_program *); #endif /* __NV50_PROG_H__ */ diff --git a/src/gallium/drivers/nouveau/nv50/nv50_push.c b/src/gallium/drivers/nouveau/nv50/nv50_push.c index a3a397c52c1..f31eaa0e314 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_push.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_push.c @@ -23,13 +23,13 @@ struct push_context { struct translate *translate; - boolean primitive_restart; + bool primitive_restart; uint32_t prim; uint32_t restart_index; uint32_t instance_id; }; -static INLINE unsigned +static inline unsigned prim_restart_search_i08(uint8_t *elts, unsigned push, uint8_t index) { unsigned i; @@ -39,7 +39,7 @@ prim_restart_search_i08(uint8_t *elts, unsigned push, uint8_t index) return i; } -static INLINE unsigned +static inline unsigned prim_restart_search_i16(uint16_t *elts, unsigned push, uint16_t index) { unsigned i; @@ -49,7 +49,7 @@ prim_restart_search_i16(uint16_t *elts, unsigned push, uint16_t index) return i; } -static INLINE unsigned +static inline unsigned prim_restart_search_i32(uint32_t *elts, unsigned push, uint32_t index) { unsigned i; @@ -179,7 +179,7 @@ emit_vertices_seq(struct push_context *ctx, unsigned start, unsigned count) #define NV50_PRIM_GL_CASE(n) \ case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n -static INLINE unsigned +static inline unsigned nv50_prim_gl(unsigned prim) { switch (prim) { @@ -212,7 +212,7 @@ nv50_push_vbo(struct nv50_context *nv50, const struct pipe_draw_info *info) unsigned i, index_size; unsigned inst_count = info->instance_count; unsigned vert_count = info->count; - boolean apply_bias = info->indexed && info->index_bias; + bool apply_bias = info->indexed && info->index_bias; ctx.push = nv50->base.pushbuf; ctx.translate = nv50->vertex->translate; @@ -258,12 +258,12 @@ nv50_push_vbo(struct nv50_context *nv50, const struct pipe_draw_info *info) NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n"); return; } - pipe->get_query_result(pipe, targ->pq, TRUE, (void *)&vert_count); + pipe->get_query_result(pipe, targ->pq, true, (void *)&vert_count); vert_count /= targ->stride; } ctx.idxbuf = NULL; index_size = 0; - ctx.primitive_restart = FALSE; + ctx.primitive_restart = false; ctx.restart_index = 0; } diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c b/src/gallium/drivers/nouveau/nv50/nv50_query.c index 81f7474e36b..f4adbf8c653 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_query.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c @@ -48,20 +48,21 @@ struct nv50_query { uint32_t base; uint32_t offset; /* base + i * 32 */ uint8_t state; - boolean is64bit; + bool is64bit; + int nesting; /* only used for occlusion queries */ struct nouveau_mm_allocation *mm; struct nouveau_fence *fence; }; #define NV50_QUERY_ALLOC_SPACE 256 -static INLINE struct nv50_query * +static inline struct nv50_query * nv50_query(struct pipe_query *pipe) { return (struct nv50_query *)pipe; } -static boolean +static bool nv50_query_allocate(struct nv50_context *nv50, struct nv50_query *q, int size) { struct nv50_screen *screen = nv50->screen; @@ -80,17 +81,17 @@ nv50_query_allocate(struct nv50_context *nv50, struct nv50_query *q, int size) if (size) { q->mm = nouveau_mm_allocate(screen->base.mm_GART, size, &q->bo, &q->base); if (!q->bo) - return FALSE; + return false; q->offset = q->base; ret = nouveau_bo_map(q->bo, 0, screen->base.client); if (ret) { nv50_query_allocate(nv50, q, 0); - return FALSE; + return false; } q->data = (uint32_t *)((uint8_t *)q->bo->map + q->base); } - return TRUE; + return true; } static void @@ -153,8 +154,8 @@ nv50_query_begin(struct pipe_context *pipe, struct pipe_query *pq) struct nv50_query *q = nv50_query(pq); /* For occlusion queries we have to change the storage, because a previous - * query might set the initial render conition to FALSE even *after* we re- - * initialized it to TRUE. + * query might set the initial render conition to false even *after* we re- + * initialized it to true. */ if (q->type == PIPE_QUERY_OCCLUSION_COUNTER) { q->offset += 32; @@ -166,7 +167,7 @@ nv50_query_begin(struct pipe_context *pipe, struct pipe_query *pq) * query ? */ q->data[0] = q->sequence; /* initialize sequence */ - q->data[1] = 1; /* initial render condition = TRUE */ + q->data[1] = 1; /* initial render condition = true */ q->data[4] = q->sequence + 1; /* for comparison COND_MODE */ q->data[5] = 0; } @@ -175,11 +176,16 @@ nv50_query_begin(struct pipe_context *pipe, struct pipe_query *pq) switch (q->type) { case PIPE_QUERY_OCCLUSION_COUNTER: - PUSH_SPACE(push, 4); - BEGIN_NV04(push, NV50_3D(COUNTER_RESET), 1); - PUSH_DATA (push, NV50_3D_COUNTER_RESET_SAMPLECNT); - BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1); - PUSH_DATA (push, 1); + q->nesting = nv50->screen->num_occlusion_queries_active++; + if (q->nesting) { + nv50_query_get(push, q, 0x10, 0x0100f002); + } else { + PUSH_SPACE(push, 4); + BEGIN_NV04(push, NV50_3D(COUNTER_RESET), 1); + PUSH_DATA (push, NV50_3D_COUNTER_RESET_SAMPLECNT); + BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1); + PUSH_DATA (push, 1); + } break; case PIPE_QUERY_PRIMITIVES_GENERATED: nv50_query_get(push, q, 0x10, 0x06805002); @@ -223,9 +229,11 @@ nv50_query_end(struct pipe_context *pipe, struct pipe_query *pq) switch (q->type) { case PIPE_QUERY_OCCLUSION_COUNTER: nv50_query_get(push, q, 0, 0x0100f002); - PUSH_SPACE(push, 2); - BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1); - PUSH_DATA (push, 0); + if (--nv50->screen->num_occlusion_queries_active == 0) { + PUSH_SPACE(push, 2); + BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1); + PUSH_DATA (push, 0); + } break; case PIPE_QUERY_PRIMITIVES_GENERATED: nv50_query_get(push, q, 0, 0x06805002); @@ -261,7 +269,7 @@ nv50_query_end(struct pipe_context *pipe, struct pipe_query *pq) nv50_query_get(push, q, 0, 0x0d005002 | (q->index << 5)); break; case PIPE_QUERY_TIMESTAMP_DISJOINT: - /* This query is not issued on GPU because disjoint is forced to FALSE */ + /* This query is not issued on GPU because disjoint is forced to false */ q->state = NV50_QUERY_STATE_READY; break; default: @@ -273,7 +281,7 @@ nv50_query_end(struct pipe_context *pipe, struct pipe_query *pq) nouveau_fence_ref(nv50->screen->base.fence.current, &q->fence); } -static INLINE void +static inline void nv50_query_update(struct nv50_query *q) { if (q->is64bit) { @@ -293,7 +301,7 @@ nv50_query_result(struct pipe_context *pipe, struct pipe_query *pq, struct nv50_query *q = nv50_query(pq); uint64_t *res64 = (uint64_t *)result; uint32_t *res32 = (uint32_t *)result; - boolean *res8 = (boolean *)result; + uint8_t *res8 = (uint8_t *)result; uint64_t *data64 = (uint64_t *)q->data; int i; @@ -307,19 +315,19 @@ nv50_query_result(struct pipe_context *pipe, struct pipe_query *pq, q->state = NV50_QUERY_STATE_FLUSHED; PUSH_KICK(nv50->base.pushbuf); } - return FALSE; + return false; } if (nouveau_bo_wait(q->bo, NOUVEAU_BO_RD, nv50->screen->base.client)) - return FALSE; + return false; } q->state = NV50_QUERY_STATE_READY; switch (q->type) { case PIPE_QUERY_GPU_FINISHED: - res8[0] = TRUE; + res8[0] = true; break; case PIPE_QUERY_OCCLUSION_COUNTER: /* u32 sequence, u32 count, u64 time */ - res64[0] = q->data[1]; + res64[0] = q->data[1] - q->data[5]; break; case PIPE_QUERY_PRIMITIVES_GENERATED: /* u64 count, u64 time */ case PIPE_QUERY_PRIMITIVES_EMITTED: /* u64 count, u64 time */ @@ -338,7 +346,7 @@ nv50_query_result(struct pipe_context *pipe, struct pipe_query *pq, break; case PIPE_QUERY_TIMESTAMP_DISJOINT: res64[0] = 1000000000; - res8[8] = FALSE; + res8[8] = false; break; case PIPE_QUERY_TIME_ELAPSED: res64[0] = data64[1] - data64[3]; @@ -347,10 +355,10 @@ nv50_query_result(struct pipe_context *pipe, struct pipe_query *pq, res32[0] = q->data[1]; break; default: - return FALSE; + return false; } - return TRUE; + return true; } void @@ -377,7 +385,7 @@ nv50_render_condition(struct pipe_context *pipe, struct nouveau_pushbuf *push = nv50->base.pushbuf; struct nv50_query *q; uint32_t cond; - boolean wait = + bool wait = mode != PIPE_RENDER_COND_NO_WAIT && mode != PIPE_RENDER_COND_BY_REGION_NO_WAIT; @@ -391,13 +399,12 @@ nv50_render_condition(struct pipe_context *pipe, case PIPE_QUERY_SO_OVERFLOW_PREDICATE: cond = condition ? NV50_3D_COND_MODE_EQUAL : NV50_3D_COND_MODE_NOT_EQUAL; - wait = TRUE; + wait = true; break; case PIPE_QUERY_OCCLUSION_COUNTER: case PIPE_QUERY_OCCLUSION_PREDICATE: if (likely(!condition)) { - /* XXX: Placeholder, handle nesting here if available */ - if (unlikely(false)) + if (unlikely(q->nesting)) cond = wait ? NV50_3D_COND_MODE_NOT_EQUAL : NV50_3D_COND_MODE_ALWAYS; else @@ -461,7 +468,7 @@ nv50_query_pushbuf_submit(struct nouveau_pushbuf *push, void nva0_so_target_save_offset(struct pipe_context *pipe, struct pipe_stream_output_target *ptarg, - unsigned index, boolean serialize) + unsigned index, bool serialize) { struct nv50_so_target *targ = nv50_so_target(ptarg); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_resource.h b/src/gallium/drivers/nouveau/nv50/nv50_resource.h index f7ee1354a92..a46e622c597 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_resource.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_resource.h @@ -35,7 +35,7 @@ nv50_screen_init_resource_functions(struct pipe_screen *pscreen); uint32_t nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz, - boolean is_3d); + bool is_3d); struct nv50_miptree_level { uint32_t offset; @@ -50,13 +50,13 @@ struct nv50_miptree { struct nv50_miptree_level level[NV50_MAX_TEXTURE_LEVELS]; uint32_t total_size; uint32_t layer_stride; - boolean layout_3d; /* TRUE if layer count varies with mip level */ + bool layout_3d; /* true if layer count varies with mip level */ uint8_t ms_x; /* log2 of number of samples in x/y dimension */ uint8_t ms_y; uint8_t ms_mode; }; -static INLINE struct nv50_miptree * +static inline struct nv50_miptree * nv50_miptree(struct pipe_resource *pt) { return (struct nv50_miptree *)pt; @@ -70,7 +70,7 @@ nv50_miptree(struct pipe_resource *pt) /* Internal functions: */ -boolean +bool nv50_miptree_init_layout_linear(struct nv50_miptree *mt, unsigned pitch_align); struct pipe_resource * @@ -98,13 +98,13 @@ struct nv50_surface { uint16_t depth; }; -static INLINE struct nv50_surface * +static inline struct nv50_surface * nv50_surface(struct pipe_surface *ps) { return (struct nv50_surface *)ps; } -static INLINE enum pipe_format +static inline enum pipe_format nv50_zs_to_s_format(enum pipe_format format) { switch (format) { diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index 6583a353578..30e6e042fbf 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -51,19 +51,19 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen, unsigned bindings) { if (sample_count > 8) - return FALSE; + return false; if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ - return FALSE; + return false; if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128) - return FALSE; + return false; if (!util_format_is_supported(format, bindings)) - return FALSE; + return false; switch (format) { case PIPE_FORMAT_Z16_UNORM: if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS) - return FALSE; + return false; break; default: break; @@ -176,6 +176,9 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CLIP_HALFZ: case PIPE_CAP_POLYGON_OFFSET_CLAMP: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: + case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: + case PIPE_CAP_DEPTH_BOUNDS_TEST: return 1; case PIPE_CAP_SEAMLESS_CUBE_MAP: return 1; /* class_3d >= NVA0_3D_CLASS; */ @@ -210,6 +213,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */ case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: + case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: return 0; case PIPE_CAP_VENDOR_ID: @@ -286,7 +290,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: /* The chip could handle more sampler views than samplers */ case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: - return MIN2(32, PIPE_MAX_SAMPLERS); + return MIN2(16, PIPE_MAX_SAMPLERS); case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: @@ -454,7 +458,7 @@ nv50_screen_init_hwctx(struct nv50_screen *screen) BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1); PUSH_DATA (push, 0xf); - if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { + if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) { BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1); PUSH_DATA (push, 0x18); } @@ -734,7 +738,7 @@ nv50_screen_create(struct nouveau_device *dev) nv50_screen_init_resource_functions(pscreen); if (screen->base.device->chipset < 0x84 || - debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) { + debug_get_bool_option("NOUVEAU_PMPEG", false)) { /* PMPEG */ nouveau_screen_init_vdec(&screen->base); } else if (screen->base.device->chipset < 0x98 || @@ -890,7 +894,7 @@ nv50_screen_create(struct nouveau_device *dev) nv50_screen_init_hwctx(screen); - nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); + nouveau_fence_new(&screen->base, &screen->base.fence.current, false); return pscreen; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h b/src/gallium/drivers/nouveau/nv50/nv50_screen.h index 881051b1862..ce51f0fc254 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h @@ -32,14 +32,14 @@ struct nv50_graph_state { uint32_t semantic_color; uint32_t semantic_psize; int32_t index_bias; - boolean uniform_buffer_bound[3]; - boolean prim_restart; - boolean point_sprite; - boolean rt_serialize; - boolean flushed; - boolean rasterizer_discard; + bool uniform_buffer_bound[3]; + bool prim_restart; + bool point_sprite; + bool rt_serialize; + bool flushed; + bool rasterizer_discard; uint8_t tls_required; - boolean new_tls_space; + bool new_tls_space; uint8_t num_vtxbufs; uint8_t num_vtxelts; uint8_t num_textures[3]; @@ -54,6 +54,8 @@ struct nv50_screen { struct nv50_context *cur_ctx; struct nv50_graph_state save_state; + int num_occlusion_queries_active; + struct nouveau_bo *code; struct nouveau_bo *uniforms; struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */ @@ -95,19 +97,19 @@ struct nv50_screen { struct nouveau_object *m2mf; }; -static INLINE struct nv50_screen * +static inline struct nv50_screen * nv50_screen(struct pipe_screen *screen) { return (struct nv50_screen *)screen; } -boolean nv50_blitter_create(struct nv50_screen *); +bool nv50_blitter_create(struct nv50_screen *); void nv50_blitter_destroy(struct nv50_screen *); int nv50_screen_tic_alloc(struct nv50_screen *, void *); int nv50_screen_tsc_alloc(struct nv50_screen *, void *); -static INLINE void +static inline void nv50_resource_fence(struct nv04_resource *res, uint32_t flags) { struct nv50_screen *screen = nv50_screen(res->base.screen); @@ -119,7 +121,7 @@ nv50_resource_fence(struct nv04_resource *res, uint32_t flags) } } -static INLINE void +static inline void nv50_resource_validate(struct nv04_resource *res, uint32_t flags) { if (likely(res->bo)) { @@ -142,21 +144,21 @@ struct nv50_format { extern const struct nv50_format nv50_format_table[]; -static INLINE void +static inline void nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry *tic) { if (tic->id >= 0) screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32)); } -static INLINE void +static inline void nv50_screen_tsc_unlock(struct nv50_screen *screen, struct nv50_tsc_entry *tsc) { if (tsc->id >= 0) screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32)); } -static INLINE void +static inline void nv50_screen_tic_free(struct nv50_screen *screen, struct nv50_tic_entry *tic) { if (tic->id >= 0) { @@ -165,7 +167,7 @@ nv50_screen_tic_free(struct nv50_screen *screen, struct nv50_tic_entry *tic) } } -static INLINE void +static inline void nv50_screen_tsc_free(struct nv50_screen *screen, struct nv50_tsc_entry *tsc) { if (tsc->id >= 0) { diff --git a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c index c698782d8bd..b033ce5c6dc 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c @@ -60,7 +60,7 @@ nv50_constbufs_validate(struct nv50_context *nv50) continue; } if (!nv50->state.uniform_buffer_bound[s]) { - nv50->state.uniform_buffer_bound[s] = TRUE; + nv50->state.uniform_buffer_bound[s] = true; BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1); PUSH_DATA (push, (b << 12) | (i << 8) | p | 1); } @@ -99,33 +99,35 @@ nv50_constbufs_validate(struct nv50_context *nv50) PUSH_DATA (push, (b << 12) | (i << 8) | p | 1); BCTX_REFN(nv50->bufctx_3d, CB(s, i), res, RD); + + nv50->cb_dirty = 1; /* Force cache flush for UBO. */ } else { BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1); PUSH_DATA (push, (i << 8) | p | 0); } if (i == 0) - nv50->state.uniform_buffer_bound[s] = FALSE; + nv50->state.uniform_buffer_bound[s] = false; } } } } -static boolean +static bool nv50_program_validate(struct nv50_context *nv50, struct nv50_program *prog) { if (!prog->translated) { prog->translated = nv50_program_translate( prog, nv50->screen->base.device->chipset); if (!prog->translated) - return FALSE; + return false; } else if (prog->mem) - return TRUE; + return true; return nv50_program_upload_code(nv50, prog); } -static INLINE void +static inline void nv50_program_update_context_state(struct nv50_context *nv50, struct nv50_program *prog, int stage) { @@ -136,7 +138,7 @@ nv50_program_update_context_state(struct nv50_context *nv50, nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TLS); if (!nv50->state.tls_required || nv50->state.new_tls_space) BCTX_REFN_bo(nv50->bufctx_3d, TLS, flags, nv50->screen->tls_bo); - nv50->state.new_tls_space = FALSE; + nv50->state.new_tls_space = false; nv50->state.tls_required |= 1 << stage; } else { if (nv50->state.tls_required == (1 << stage)) @@ -243,11 +245,11 @@ nv50_sprite_coords_validate(struct nv50_context *nv50) for (i = 0; i < 8; ++i) PUSH_DATA(push, 0); - nv50->state.point_sprite = FALSE; + nv50->state.point_sprite = false; } return; } else { - nv50->state.point_sprite = TRUE; + nv50->state.point_sprite = true; } memset(pntc, 0, sizeof(pntc)); @@ -646,7 +648,7 @@ nv50_stream_output_validate(struct nv50_context *nv50) nv50_query_pushbuf_submit(push, targ->pq, 0x4); } else { PUSH_DATA(push, 0); - targ->clean = FALSE; + targ->clean = false; } } else { const unsigned limit = targ->pipe.buffer_size / diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state.c b/src/gallium/drivers/nouveau/nv50/nv50_state.c index d4d41af3c61..9505a0b4085 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_state.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_state.c @@ -62,7 +62,7 @@ * in advance to maintain elegant separate shader objects.) */ -static INLINE uint32_t +static inline uint32_t nv50_colormask(unsigned mask) { uint32_t ret = 0; @@ -82,7 +82,7 @@ nv50_colormask(unsigned mask) #define NV50_BLEND_FACTOR_CASE(a, b) \ case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b -static INLINE uint32_t +static inline uint32_t nv50_blend_fac(unsigned factor) { switch (factor) { @@ -116,7 +116,7 @@ nv50_blend_state_create(struct pipe_context *pipe, { struct nv50_blend_stateobj *so = CALLOC_STRUCT(nv50_blend_stateobj); int i; - boolean emit_common_func = cso->rt[0].blend_enable; + bool emit_common_func = cso->rt[0].blend_enable; uint32_t ms; if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) { @@ -137,11 +137,11 @@ nv50_blend_state_create(struct pipe_context *pipe, for (i = 0; i < 8; ++i) { SB_DATA(so, cso->rt[i].blend_enable); if (cso->rt[i].blend_enable) - emit_common_func = TRUE; + emit_common_func = true; } if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) { - emit_common_func = FALSE; + emit_common_func = false; for (i = 0; i < 8; ++i) { if (!cso->rt[i].blend_enable) @@ -373,6 +373,16 @@ nv50_zsa_state_create(struct pipe_context *pipe, SB_DATA (so, 0); } + SB_BEGIN_3D(so, DEPTH_BOUNDS_EN, 1); + if (cso->depth.bounds_test) { + SB_DATA (so, 1); + SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2); + SB_DATA (so, fui(cso->depth.bounds_min)); + SB_DATA (so, fui(cso->depth.bounds_max)); + } else { + SB_DATA (so, 0); + } + if (cso->stencil[0].enabled) { SB_BEGIN_3D(so, STENCIL_ENABLE, 5); SB_DATA (so, 1); @@ -439,7 +449,7 @@ nv50_zsa_state_delete(struct pipe_context *pipe, void *hwcso) #define NV50_TSC_WRAP_CASE(n) \ case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n -static INLINE unsigned +static inline unsigned nv50_tsc_wrap_mode(unsigned wrap) { switch (wrap) { @@ -572,7 +582,7 @@ nv50_sampler_state_delete(struct pipe_context *pipe, void *hwcso) FREE(hwcso); } -static INLINE void +static inline void nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s, unsigned nr, void **hwcso) { @@ -650,7 +660,7 @@ nv50_sampler_view_destroy(struct pipe_context *pipe, FREE(nv50_tic_entry(view)); } -static INLINE void +static inline void nv50_stage_set_sampler_views(struct nv50_context *nv50, int s, unsigned nr, struct pipe_sampler_view **views) @@ -808,7 +818,7 @@ nv50_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, pipe_resource_reference(&nv50->constbuf[s][i].u.buf, res); - nv50->constbuf[s][i].user = (cb && cb->user_buffer) ? TRUE : FALSE; + nv50->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false; if (nv50->constbuf[s][i].user) { nv50->constbuf[s][i].u.data = cb->user_buffer; nv50->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000); @@ -1041,7 +1051,7 @@ nv50_so_target_create(struct pipe_context *pipe, } else { targ->pq = NULL; } - targ->clean = TRUE; + targ->clean = true; targ->pipe.buffer_size = size; targ->pipe.buffer_offset = offset; @@ -1075,32 +1085,32 @@ nv50_set_stream_output_targets(struct pipe_context *pipe, { struct nv50_context *nv50 = nv50_context(pipe); unsigned i; - boolean serialize = TRUE; - const boolean can_resume = nv50->screen->base.class_3d >= NVA0_3D_CLASS; + bool serialize = true; + const bool can_resume = nv50->screen->base.class_3d >= NVA0_3D_CLASS; assert(num_targets <= 4); for (i = 0; i < num_targets; ++i) { - const boolean changed = nv50->so_target[i] != targets[i]; - const boolean append = (offsets[i] == (unsigned)-1); + const bool changed = nv50->so_target[i] != targets[i]; + const bool append = (offsets[i] == (unsigned)-1); if (!changed && append) continue; nv50->so_targets_dirty |= 1 << i; if (can_resume && changed && nv50->so_target[i]) { nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize); - serialize = FALSE; + serialize = false; } if (targets[i] && !append) - nv50_so_target(targets[i])->clean = TRUE; + nv50_so_target(targets[i])->clean = true; pipe_so_target_reference(&nv50->so_target[i], targets[i]); } for (; i < nv50->num_so_targets; ++i) { if (can_resume && nv50->so_target[i]) { nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize); - serialize = FALSE; + serialize = false; } pipe_so_target_reference(&nv50->so_target[i], NULL); nv50->so_targets_dirty |= 1 << i; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c index 116bf4bba7c..985603df5fa 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c @@ -2,7 +2,7 @@ #include "nv50/nv50_context.h" #include "nv50/nv50_defs.xml.h" -static INLINE void +static inline void nv50_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i) { BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 4); @@ -82,7 +82,7 @@ nv50_validate_fb(struct nv50_context *nv50) ms_mode = mt->ms_mode; if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) - nv50->state.rt_serialize = TRUE; + nv50->state.rt_serialize = true; mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING; @@ -111,7 +111,7 @@ nv50_validate_fb(struct nv50_context *nv50) ms_mode = mt->ms_mode; if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) - nv50->state.rt_serialize = TRUE; + nv50->state.rt_serialize = true; mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING; @@ -275,7 +275,7 @@ nv50_validate_viewport(struct nv50_context *nv50) nv50->viewports_dirty = 0; } -static INLINE void +static inline void nv50_check_program_ucps(struct nv50_context *nv50, struct nv50_program *vp, uint8_t mask) { @@ -296,6 +296,23 @@ nv50_check_program_ucps(struct nv50_context *nv50, nv50_fp_linkage_validate(nv50); } +/* alpha test is disabled if there are no color RTs, so make sure we have at + * least one if alpha test is enabled. Note that this must run after + * nv50_validate_fb, otherwise that will override the RT count setting. + */ +static void +nv50_validate_derived_2(struct nv50_context *nv50) +{ + struct nouveau_pushbuf *push = nv50->base.pushbuf; + + if (nv50->zsa && nv50->zsa->pipe.alpha.enabled && + nv50->framebuffer.nr_cbufs == 0) { + nv50_fb_set_null_rt(push, 0); + BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1); + PUSH_DATA (push, (076543210 << 4) | 1); + } +} + static void nv50_validate_clip(struct nv50_context *nv50) { @@ -456,6 +473,7 @@ static struct state_validate { { nv50_gp_linkage_validate, NV50_NEW_GMTYPROG | NV50_NEW_VERTPROG }, { nv50_validate_derived_rs, NV50_NEW_FRAGPROG | NV50_NEW_RASTERIZER | NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG }, + { nv50_validate_derived_2, NV50_NEW_ZSA | NV50_NEW_FRAMEBUFFER }, { nv50_validate_clip, NV50_NEW_CLIP | NV50_NEW_RASTERIZER | NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG }, { nv50_constbufs_validate, NV50_NEW_CONSTBUF }, @@ -468,7 +486,7 @@ static struct state_validate { }; #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0])) -boolean +bool nv50_state_validate(struct nv50_context *nv50, uint32_t mask, unsigned words) { uint32_t state_mask; @@ -490,19 +508,19 @@ nv50_state_validate(struct nv50_context *nv50, uint32_t mask, unsigned words) nv50->dirty &= ~state_mask; if (nv50->state.rt_serialize) { - nv50->state.rt_serialize = FALSE; + nv50->state.rt_serialize = false; BEGIN_NV04(nv50->base.pushbuf, SUBC_3D(NV50_GRAPH_SERIALIZE), 1); PUSH_DATA (nv50->base.pushbuf, 0); } - nv50_bufctx_fence(nv50->bufctx_3d, FALSE); + nv50_bufctx_fence(nv50->bufctx_3d, false); } nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx_3d); ret = nouveau_pushbuf_validate(nv50->base.pushbuf); if (unlikely(nv50->state.flushed)) { - nv50->state.flushed = FALSE; - nv50_bufctx_fence(nv50->bufctx_3d, TRUE); + nv50->state.flushed = false; + nv50_bufctx_fence(nv50->bufctx_3d, true); } return !ret; } diff --git a/src/gallium/drivers/nouveau/nv50/nv50_stateobj.h b/src/gallium/drivers/nouveau/nv50/nv50_stateobj.h index eea5327b6cb..cf75d1eb11b 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_stateobj.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_stateobj.h @@ -31,7 +31,7 @@ struct nv50_rasterizer_stateobj { struct nv50_zsa_stateobj { struct pipe_depth_stencil_alpha_state pipe; int size; - uint32_t state[29]; + uint32_t state[34]; }; struct nv50_constbuf { @@ -41,7 +41,7 @@ struct nv50_constbuf { } u; uint32_t size; /* max 65536 */ uint32_t offset; - boolean user; /* should only be TRUE if u.data is valid and non-NULL */ + bool user; /* should only be true if u.data is valid and non-NULL */ }; struct nv50_vertex_element { @@ -56,7 +56,7 @@ struct nv50_vertex_stateobj { unsigned num_elements; uint32_t instance_elts; uint32_t instance_bufs; - boolean need_conversion; + bool need_conversion; unsigned vertex_size; unsigned packet_vertex_limit; struct nv50_vertex_element element[0]; @@ -66,10 +66,10 @@ struct nv50_so_target { struct pipe_stream_output_target pipe; struct pipe_query *pq; unsigned stride; - boolean clean; + bool clean; }; -static INLINE struct nv50_so_target * +static inline struct nv50_so_target * nv50_so_target(struct pipe_stream_output_target *ptarg) { return (struct nv50_so_target *)ptarg; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_stateobj_tex.h b/src/gallium/drivers/nouveau/nv50/nv50_stateobj_tex.h index 99548cbdb42..e0793bb6ec4 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_stateobj_tex.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_stateobj_tex.h @@ -9,7 +9,7 @@ struct nv50_tsc_entry { uint32_t tsc[8]; }; -static INLINE struct nv50_tsc_entry * +static inline struct nv50_tsc_entry * nv50_tsc_entry(void *hwcso) { return (struct nv50_tsc_entry *)hwcso; @@ -21,7 +21,7 @@ struct nv50_tic_entry { uint32_t tic[8]; }; -static INLINE struct nv50_tic_entry * +static inline struct nv50_tic_entry * nv50_tic_entry(struct pipe_sampler_view *view) { return (struct nv50_tic_entry *)view; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c index dc9852d4e47..b1ae01692cb 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c @@ -49,8 +49,8 @@ #define NOUVEAU_DRIVER 0x50 #include "nv50/nv50_blit.h" -static INLINE uint8_t -nv50_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal) +static inline uint8_t +nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal) { uint8_t id = nv50_format_table[format].rt; @@ -76,7 +76,7 @@ nv50_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal) static int nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst, struct nv50_miptree *mt, unsigned level, unsigned layer, - enum pipe_format pformat, boolean dst_src_pformat_equal) + enum pipe_format pformat, bool dst_src_pformat_equal) { struct nouveau_bo *bo = mt->base.bo; uint32_t width, height, depth; @@ -153,7 +153,7 @@ nv50_2d_texture_do_copy(struct nouveau_pushbuf *push, const enum pipe_format dfmt = dst->base.base.format; const enum pipe_format sfmt = src->base.base.format; int ret; - boolean eqfmt = dfmt == sfmt; + bool eqfmt = dfmt == sfmt; if (!PUSH_SPACE(push, 2 * 16 + 32)) return PIPE_ERROR; @@ -196,7 +196,7 @@ nv50_resource_copy_region(struct pipe_context *pipe, { struct nv50_context *nv50 = nv50_context(pipe); int ret; - boolean m2mf; + bool m2mf; unsigned dst_layer = dstz, src_layer = src_box->z; if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { @@ -658,7 +658,7 @@ nv50_blitter_make_vp(struct nv50_blitter *blit) }; blit->vp.type = PIPE_SHADER_VERTEX; - blit->vp.translated = TRUE; + blit->vp.translated = true; blit->vp.code = (uint32_t *)code; /* const_cast */ blit->vp.code_size = sizeof(code); blit->vp.max_gpr = 4; @@ -687,24 +687,24 @@ nv50_blitter_make_fp(struct pipe_context *pipe, const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg); - boolean tex_rgbaz = FALSE; - boolean tex_s = FALSE; - boolean cvt_un8 = FALSE; + bool tex_rgbaz = false; + bool tex_s = false; + bool cvt_un8 = false; if (mode != NV50_BLIT_MODE_PASS && mode != NV50_BLIT_MODE_Z24X8 && mode != NV50_BLIT_MODE_X8Z24) - tex_s = TRUE; + tex_s = true; if (mode != NV50_BLIT_MODE_X24S8 && mode != NV50_BLIT_MODE_S8X24 && mode != NV50_BLIT_MODE_XS) - tex_rgbaz = TRUE; + tex_rgbaz = true; if (mode != NV50_BLIT_MODE_PASS && mode != NV50_BLIT_MODE_ZS && mode != NV50_BLIT_MODE_XS) - cvt_un8 = TRUE; + cvt_un8 = true; ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); if (!ureg) @@ -1271,7 +1271,7 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info) int i; uint32_t mode; uint32_t mask = nv50_blit_eng2d_get_mask(info); - boolean b; + bool b; mode = nv50_blit_get_filter(info) ? NV50_2D_BLIT_CONTROL_FILTER_BILINEAR : @@ -1410,7 +1410,7 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info) PUSH_DATA (push, srcy >> 32); } } - nv50_bufctx_fence(nv50->bufctx, FALSE); + nv50_bufctx_fence(nv50->bufctx, false); nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D); @@ -1432,71 +1432,82 @@ static void nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info) { struct nv50_context *nv50 = nv50_context(pipe); - boolean eng3d = FALSE; + struct nouveau_pushbuf *push = nv50->base.pushbuf; + bool eng3d = FALSE; if (util_format_is_depth_or_stencil(info->dst.resource->format)) { if (!(info->mask & PIPE_MASK_ZS)) return; if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT || info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) - eng3d = TRUE; + eng3d = true; if (info->filter != PIPE_TEX_FILTER_NEAREST) - eng3d = TRUE; + eng3d = true; } else { if (!(info->mask & PIPE_MASK_RGBA)) return; if (info->mask != PIPE_MASK_RGBA) - eng3d = TRUE; + eng3d = true; } if (nv50_miptree(info->src.resource)->layout_3d) { - eng3d = TRUE; + eng3d = true; } else if (info->src.box.depth != info->dst.box.depth) { - eng3d = TRUE; + eng3d = true; debug_printf("blit: cannot filter array or cube textures in z direction"); } if (!eng3d && info->dst.format != info->src.format) { if (!nv50_2d_dst_format_faithful(info->dst.format) || !nv50_2d_src_format_faithful(info->src.format)) { - eng3d = TRUE; + eng3d = true; } else if (!nv50_2d_src_format_faithful(info->src.format)) { if (!util_format_is_luminance(info->src.format)) { if (util_format_is_intensity(info->src.format)) - eng3d = TRUE; + eng3d = true; else if (!nv50_2d_dst_format_ops_supported(info->dst.format)) - eng3d = TRUE; + eng3d = true; else eng3d = !nv50_2d_format_supported(info->src.format); } } else if (util_format_is_luminance_alpha(info->src.format)) - eng3d = TRUE; + eng3d = true; } if (info->src.resource->nr_samples == 8 && info->dst.resource->nr_samples <= 1) - eng3d = TRUE; + eng3d = true; /* FIXME: can't make this work with eng2d anymore */ if ((info->src.resource->nr_samples | 1) != (info->dst.resource->nr_samples | 1)) - eng3d = TRUE; + eng3d = true; /* FIXME: find correct src coordinate adjustments */ if ((info->src.box.width != info->dst.box.width && info->src.box.width != -info->dst.box.width) || (info->src.box.height != info->dst.box.height && info->src.box.height != -info->dst.box.height)) - eng3d = TRUE; + eng3d = true; + + if (nv50->screen->num_occlusion_queries_active) { + BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1); + PUSH_DATA (push, 0); + } if (!eng3d) nv50_blit_eng2d(nv50, info); else nv50_blit_3d(nv50, info); + + if (nv50->screen->num_occlusion_queries_active) { + BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1); + PUSH_DATA (push, 1); + } } static void @@ -1505,13 +1516,13 @@ nv50_flush_resource(struct pipe_context *ctx, { } -boolean +bool nv50_blitter_create(struct nv50_screen *screen) { screen->blitter = CALLOC_STRUCT(nv50_blitter); if (!screen->blitter) { NOUVEAU_ERR("failed to allocate blitter struct\n"); - return FALSE; + return false; } pipe_mutex_init(screen->blitter->mutex); @@ -1519,7 +1530,7 @@ nv50_blitter_create(struct nv50_screen *screen) nv50_blitter_make_vp(screen->blitter); nv50_blitter_make_sampler(screen->blitter); - return TRUE; + return true; } void @@ -1542,20 +1553,20 @@ nv50_blitter_destroy(struct nv50_screen *screen) FREE(blitter); } -boolean +bool nv50_blitctx_create(struct nv50_context *nv50) { nv50->blit = CALLOC_STRUCT(nv50_blitctx); if (!nv50->blit) { NOUVEAU_ERR("failed to allocate blit context\n"); - return FALSE; + return false; } nv50->blit->nv50 = nv50; nv50->blit->rast.pipe.half_pixel_center = 1; - return TRUE; + return true; } void diff --git a/src/gallium/drivers/nouveau/nv50/nv50_tex.c b/src/gallium/drivers/nouveau/nv50/nv50_tex.c index d69c8d6ff0d..fc6374d1b1b 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_tex.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_tex.c @@ -31,8 +31,8 @@ (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK | \ NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK) -static INLINE uint32_t -nv50_tic_swizzle(uint32_t tc, unsigned swz, boolean tex_int) +static inline uint32_t +nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int) { switch (swz) { case PIPE_SWIZZLE_RED: @@ -71,6 +71,7 @@ nv50_create_texture_view(struct pipe_context *pipe, uint32_t flags, enum pipe_texture_target target) { + const uint32_t class_3d = nouveau_context(pipe)->screen->class_3d; const struct util_format_description *desc; uint64_t addr; uint32_t *tic; @@ -78,7 +79,7 @@ nv50_create_texture_view(struct pipe_context *pipe, uint32_t depth; struct nv50_tic_entry *view; struct nv50_miptree *mt = nv50_miptree(texture); - boolean tex_int; + bool tex_int; view = MALLOC_STRUCT(nv50_tic_entry); if (!view) @@ -192,7 +193,7 @@ nv50_create_texture_view(struct pipe_context *pipe, break; default: NOUVEAU_ERR("invalid texture target: %d\n", mt->base.base.target); - return FALSE; + return false; } tic[3] = (flags & NV50_TEXVIEW_FILTER_MSAA8) ? 0x20000000 : 0x00300000; @@ -201,11 +202,17 @@ nv50_create_texture_view(struct pipe_context *pipe, tic[5] = (mt->base.base.height0 << mt->ms_y) & 0xffff; tic[5] |= depth << 16; - tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT; + if (class_3d > NV50_3D_CLASS) + tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT; + else + tic[5] |= view->pipe.u.tex.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT; tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000; /* sampling points */ - tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level; + if (class_3d > NV50_3D_CLASS) + tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level; + else + tic[7] = 0; if (unlikely(!(tic[2] & NV50_TIC_2_NORMALIZED_COORDS))) if (mt->base.base.last_level) @@ -214,13 +221,13 @@ nv50_create_texture_view(struct pipe_context *pipe, return &view->pipe; } -static boolean +static bool nv50_validate_tic(struct nv50_context *nv50, int s) { struct nouveau_pushbuf *push = nv50->base.pushbuf; struct nouveau_bo *txc = nv50->screen->txc; unsigned i; - boolean need_flush = FALSE; + bool need_flush = false; assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS); for (i = 0; i < nv50->num_textures[s]; ++i) { @@ -263,7 +270,7 @@ nv50_validate_tic(struct nv50_context *nv50, int s) BEGIN_NI04(push, NV50_2D(SIFC_DATA), 8); PUSH_DATAp(push, &tic->tic[0], 8); - need_flush = TRUE; + need_flush = true; } else if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1); @@ -309,7 +316,7 @@ nv50_validate_tic(struct nv50_context *nv50, int s) void nv50_validate_textures(struct nv50_context *nv50) { - boolean need_flush; + bool need_flush; need_flush = nv50_validate_tic(nv50, 0); need_flush |= nv50_validate_tic(nv50, 1); @@ -321,12 +328,12 @@ void nv50_validate_textures(struct nv50_context *nv50) } } -static boolean +static bool nv50_validate_tsc(struct nv50_context *nv50, int s) { struct nouveau_pushbuf *push = nv50->base.pushbuf; unsigned i; - boolean need_flush = FALSE; + bool need_flush = false; assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS); for (i = 0; i < nv50->num_samplers[s]; ++i) { @@ -343,7 +350,7 @@ nv50_validate_tsc(struct nv50_context *nv50, int s) nv50_sifc_linear_u8(&nv50->base, nv50->screen->txc, 65536 + tsc->id * 32, NOUVEAU_BO_VRAM, 32, tsc->tsc); - need_flush = TRUE; + need_flush = true; } nv50->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32); @@ -361,7 +368,7 @@ nv50_validate_tsc(struct nv50_context *nv50, int s) void nv50_validate_samplers(struct nv50_context *nv50) { - boolean need_flush; + bool need_flush; need_flush = nv50_validate_tsc(nv50, 0); need_flush |= nv50_validate_tsc(nv50, 1); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c index 1fd33b8aa59..6324726acec 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c @@ -58,7 +58,7 @@ nv50_vertex_state_create(struct pipe_context *pipe, so->num_elements = num_elements; so->instance_elts = 0; so->instance_bufs = 0; - so->need_conversion = FALSE; + so->need_conversion = false; memset(so->vb_access_size, 0, sizeof(so->vb_access_size)); @@ -89,7 +89,7 @@ nv50_vertex_state_create(struct pipe_context *pipe, return NULL; } so->element[i].state = nv50_format_table[fmt].vtx; - so->need_conversion = TRUE; + so->need_conversion = true; } so->element[i].state |= i; @@ -188,7 +188,7 @@ nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb, } } -static INLINE void +static inline void nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi, uint32_t *base, uint32_t *size) { @@ -229,7 +229,7 @@ nv50_upload_user_buffers(struct nv50_context *nv50, BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART | NOUVEAU_BO_RD, bo); } - nv50->base.vbo_dirty = TRUE; + nv50->base.vbo_dirty = true; } static void @@ -275,10 +275,10 @@ nv50_update_user_vbufs(struct nv50_context *nv50) PUSH_DATAh(push, address[b] + ve->src_offset); PUSH_DATA (push, address[b] + ve->src_offset); } - nv50->base.vbo_dirty = TRUE; + nv50->base.vbo_dirty = true; } -static INLINE void +static inline void nv50_release_user_vbufs(struct nv50_context *nv50) { if (nv50->vbo_user) { @@ -316,7 +316,7 @@ nv50_vertex_arrays_validate(struct nv50_context *nv50) struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer); if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; - nv50->base.vbo_dirty = TRUE; + nv50->base.vbo_dirty = true; break; } } @@ -382,6 +382,11 @@ nv50_vertex_arrays_validate(struct nv50_context *nv50) if (nv50->vbo_user & (1 << b)) { address = addrs[b] + ve->pipe.src_offset; limit = addrs[b] + limits[b]; + } else + if (!vb->buffer) { + BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); + PUSH_DATA (push, 0); + continue; } else { struct nv04_resource *buf = nv04_resource(vb->buffer); if (!(refd & (1 << b))) { @@ -418,7 +423,7 @@ nv50_vertex_arrays_validate(struct nv50_context *nv50) #define NV50_PRIM_GL_CASE(n) \ case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n -static INLINE unsigned +static inline unsigned nv50_prim_gl(unsigned prim) { switch (prim) { @@ -585,7 +590,7 @@ nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push, } static void -nv50_draw_elements(struct nv50_context *nv50, boolean shorten, +nv50_draw_elements(struct nv50_context *nv50, bool shorten, unsigned mode, unsigned start, unsigned count, unsigned instance_count, int32_t index_bias) { @@ -746,9 +751,9 @@ nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan) { struct nv50_screen *screen = chan->user_priv; - nouveau_fence_update(&screen->base, TRUE); + nouveau_fence_update(&screen->base, true); - nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, TRUE); + nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true); } void @@ -801,7 +806,7 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) continue; if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) - nv50->cb_dirty = TRUE; + nv50->cb_dirty = true; } } @@ -809,7 +814,7 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) if (nv50->cb_dirty) { BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1); PUSH_DATA (push, 0); - nv50->cb_dirty = FALSE; + nv50->cb_dirty = false; } if (nv50->vbo_fifo) { @@ -830,21 +835,21 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) if (!nv50->vtxbuf[i].buffer) continue; if (nv50->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) - nv50->base.vbo_dirty = TRUE; + nv50->base.vbo_dirty = true; } if (!nv50->base.vbo_dirty && nv50->idxbuf.buffer && nv50->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) - nv50->base.vbo_dirty = TRUE; + nv50->base.vbo_dirty = true; if (nv50->base.vbo_dirty) { BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1); PUSH_DATA (push, 0); - nv50->base.vbo_dirty = FALSE; + nv50->base.vbo_dirty = false; } if (info->indexed) { - boolean shorten = info->max_index <= 65535; + bool shorten = info->max_index <= 65535; if (info->primitive_restart != nv50->state.prim_restart) { if (info->primitive_restart) { @@ -853,7 +858,7 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) PUSH_DATA (push, info->restart_index); if (info->restart_index > 65535) - shorten = FALSE; + shorten = false; } else { BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1); PUSH_DATA (push, 0); @@ -865,7 +870,7 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) PUSH_DATA (push, info->restart_index); if (info->restart_index > 65535) - shorten = FALSE; + shorten = false; } nv50_draw_elements(nv50, shorten, diff --git a/src/gallium/drivers/nouveau/nv50/nv50_winsys.h b/src/gallium/drivers/nouveau/nv50/nv50_winsys.h index e8578c8be6f..76f1b41ea70 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_winsys.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_winsys.h @@ -16,14 +16,14 @@ #endif -static INLINE void +static inline void nv50_add_bufctx_resident_bo(struct nouveau_bufctx *bufctx, int bin, unsigned flags, struct nouveau_bo *bo) { nouveau_bufctx_refn(bufctx, bin, bo, flags)->priv = NULL; } -static INLINE void +static inline void nv50_add_bufctx_resident(struct nouveau_bufctx *bufctx, int bin, struct nv04_resource *res, unsigned flags) { @@ -39,7 +39,7 @@ nv50_add_bufctx_resident(struct nouveau_bufctx *bufctx, int bin, #define BCTX_REFN(bctx, bin, res, acc) \ nv50_add_bufctx_resident(bctx, NV50_BIND_##bin, res, NOUVEAU_BO_##acc) -static INLINE void +static inline void PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) { struct nouveau_pushbuf_refn ref = { bo, flags }; @@ -61,39 +61,39 @@ PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) #define NV50_COMPUTE(n) SUBC_COMPUTE(NV50_COMPUTE_##n) -static INLINE uint32_t +static inline uint32_t NV50_FIFO_PKHDR(int subc, int mthd, unsigned size) { return 0x00000000 | (size << 18) | (subc << 13) | mthd; } -static INLINE uint32_t +static inline uint32_t NV50_FIFO_PKHDR_NI(int subc, int mthd, unsigned size) { return 0x40000000 | (size << 18) | (subc << 13) | mthd; } -static INLINE uint32_t +static inline uint32_t NV50_FIFO_PKHDR_L(int subc, int mthd) { return 0x00030000 | (subc << 13) | mthd; } -static INLINE uint32_t +static inline uint32_t nouveau_bo_memtype(const struct nouveau_bo *bo) { return bo->config.nv50.memtype; } -static INLINE void +static inline void PUSH_DATAh(struct nouveau_pushbuf *push, uint64_t data) { *push->cur++ = (uint32_t)(data >> 32); } -static INLINE void +static inline void BEGIN_NV04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) { #ifndef NV50_PUSH_EXPLICIT_SPACE_CHECKING @@ -102,7 +102,7 @@ BEGIN_NV04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) PUSH_DATA (push, NV50_FIFO_PKHDR(subc, mthd, size)); } -static INLINE void +static inline void BEGIN_NI04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) { #ifndef NV50_PUSH_EXPLICIT_SPACE_CHECKING @@ -112,7 +112,7 @@ BEGIN_NI04(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) } /* long, non-incremental, nv50-only */ -static INLINE void +static inline void BEGIN_NL50(struct nouveau_pushbuf *push, int subc, int mthd, uint32_t size) { #ifndef NV50_PUSH_EXPLICIT_SPACE_CHECKING diff --git a/src/gallium/drivers/nouveau/nv50/nv84_video.h b/src/gallium/drivers/nouveau/nv50/nv84_video.h index 2edba389dbf..09773c12974 100644 --- a/src/gallium/drivers/nouveau/nv50/nv84_video.h +++ b/src/gallium/drivers/nouveau/nv50/nv84_video.h @@ -102,12 +102,12 @@ struct nv84_decoder { uint8_t mpeg12_non_intra_matrix[64]; }; -static INLINE uint32_t mb(uint32_t coord) +static inline uint32_t mb(uint32_t coord) { return (coord + 0xf)>>4; } -static INLINE uint32_t mb_half(uint32_t coord) +static inline uint32_t mb_half(uint32_t coord) { return (coord + 0x1f)>>5; } diff --git a/src/gallium/drivers/nouveau/nv50/nv84_video_vp.c b/src/gallium/drivers/nouveau/nv50/nv84_video_vp.c index f3480b2e00e..8b121477a37 100644 --- a/src/gallium/drivers/nouveau/nv50/nv84_video_vp.c +++ b/src/gallium/drivers/nouveau/nv50/nv84_video_vp.c @@ -221,7 +221,7 @@ nv84_decoder_vp_h264(struct nv84_decoder *dec, PUSH_KICK (push); } -static INLINE int16_t inverse_quantize(int16_t val, uint8_t quant, int mpeg1) { +static inline int16_t inverse_quantize(int16_t val, uint8_t quant, int mpeg1) { int16_t ret = val * quant / 16; if (mpeg1 && ret) { if (ret > 0) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c index 56fc83d3679..47bd123621b 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c @@ -121,51 +121,51 @@ nvc0_screen_compute_setup(struct nvc0_screen *screen, return 0; } -boolean +bool nvc0_compute_validate_program(struct nvc0_context *nvc0) { struct nvc0_program *prog = nvc0->compprog; if (prog->mem) - return TRUE; + return true; if (!prog->translated) { prog->translated = nvc0_program_translate( prog, nvc0->screen->base.device->chipset); if (!prog->translated) - return FALSE; + return false; } if (unlikely(!prog->code_size)) - return FALSE; + return false; if (likely(prog->code_size)) { if (nvc0_program_upload_code(nvc0, prog)) { struct nouveau_pushbuf *push = nvc0->base.pushbuf; BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1); PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CODE); - return TRUE; + return true; } } - return FALSE; + return false; } -static boolean +static bool nvc0_compute_state_validate(struct nvc0_context *nvc0) { if (!nvc0_compute_validate_program(nvc0)) - return FALSE; + return false; /* TODO: textures, samplers, surfaces, global memory buffers */ - nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, FALSE); + nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, false); nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_cp); if (unlikely(nouveau_pushbuf_validate(nvc0->base.pushbuf))) - return FALSE; + return false; if (unlikely(nvc0->state.flushed)) - nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, TRUE); + nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true); - return TRUE; + return true; } diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h index 9a1a71760d7..168a6d1bee2 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h @@ -4,7 +4,7 @@ #include "nv50/nv50_defs.xml.h" #include "nvc0/nvc0_compute.xml.h" -boolean +bool nvc0_compute_validate_program(struct nvc0_context *nvc0); #endif /* NVC0_COMPUTE_H */ diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c index a35c3f66142..84f8db6a8ac 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c @@ -63,12 +63,12 @@ nvc0_memory_barrier(struct pipe_context *pipe, unsigned flags) if (!nvc0->vtxbuf[i].buffer) continue; if (nvc0->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) - nvc0->base.vbo_dirty = TRUE; + nvc0->base.vbo_dirty = true; } if (nvc0->idxbuf.buffer && nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) - nvc0->base.vbo_dirty = TRUE; + nvc0->base.vbo_dirty = true; for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) { uint32_t valid = nvc0->constbuf_valid[s]; @@ -86,7 +86,7 @@ nvc0_memory_barrier(struct pipe_context *pipe, unsigned flags) continue; if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) - nvc0->cb_dirty = TRUE; + nvc0->cb_dirty = true; } } } @@ -164,9 +164,9 @@ nvc0_default_kick_notify(struct nouveau_pushbuf *push) if (screen) { nouveau_fence_next(&screen->base); - nouveau_fence_update(&screen->base, TRUE); + nouveau_fence_update(&screen->base, true); if (screen->cur_ctx) - screen->cur_ctx->state.flushed = TRUE; + screen->cur_ctx->state.flushed = true; NOUVEAU_DRV_STAT(&screen->base, pushbuf_count, 1); } } @@ -378,7 +378,7 @@ out_err: void nvc0_bufctx_fence(struct nvc0_context *nvc0, struct nouveau_bufctx *bufctx, - boolean on_flush) + bool on_flush) { struct nouveau_list *list = on_flush ? &bufctx->current : &bufctx->pending; struct nouveau_list *it; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h index a8d7593b398..f4499423a10 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h @@ -54,6 +54,7 @@ #define NVC0_NEW_IDXBUF (1 << 22) #define NVC0_NEW_SURFACES (1 << 23) #define NVC0_NEW_MIN_SAMPLES (1 << 24) +#define NVC0_NEW_TESSFACTOR (1 << 25) #define NVC0_NEW_CP_PROGRAM (1 << 0) #define NVC0_NEW_CP_SURFACES (1 << 1) @@ -93,7 +94,7 @@ struct nvc0_blitctx; -boolean nvc0_blitctx_create(struct nvc0_context *); +bool nvc0_blitctx_create(struct nvc0_context *); void nvc0_blitctx_destroy(struct nvc0_context *); struct nvc0_context { @@ -130,7 +131,7 @@ struct nvc0_context { struct nvc0_constbuf constbuf[6][NVC0_MAX_PIPE_CONSTBUFS]; uint16_t constbuf_dirty[6]; uint16_t constbuf_valid[6]; - boolean cb_dirty; + bool cb_dirty; struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS]; unsigned num_vtxbufs; @@ -164,14 +165,17 @@ struct nvc0_context { unsigned sample_mask; unsigned min_samples; - boolean vbo_push_hint; + float default_tess_outer[4]; + float default_tess_inner[2]; + + bool vbo_push_hint; uint8_t tfbbuf_dirty; struct pipe_stream_output_target *tfbbuf[4]; unsigned num_tfbbufs; struct pipe_query *cond_query; - boolean cond_cond; /* inverted rendering condition */ + bool cond_cond; /* inverted rendering condition */ uint cond_mode; uint32_t cond_condmode; /* the calculated condition */ @@ -184,19 +188,19 @@ struct nvc0_context { struct util_dynarray global_residents; }; -static INLINE struct nvc0_context * +static inline struct nvc0_context * nvc0_context(struct pipe_context *pipe) { return (struct nvc0_context *)pipe; } -static INLINE unsigned +static inline unsigned nvc0_shader_stage(unsigned pipe) { switch (pipe) { case PIPE_SHADER_VERTEX: return 0; -/* case PIPE_SHADER_TESSELLATION_CONTROL: return 1; */ -/* case PIPE_SHADER_TESSELLATION_EVALUATION: return 2; */ + case PIPE_SHADER_TESS_CTRL: return 1; + case PIPE_SHADER_TESS_EVAL: return 2; case PIPE_SHADER_GEOMETRY: return 3; case PIPE_SHADER_FRAGMENT: return 4; case PIPE_SHADER_COMPUTE: return 5; @@ -210,15 +214,15 @@ nvc0_shader_stage(unsigned pipe) /* nvc0_context.c */ struct pipe_context *nvc0_create(struct pipe_screen *, void *); void nvc0_bufctx_fence(struct nvc0_context *, struct nouveau_bufctx *, - boolean on_flush); + bool on_flush); void nvc0_default_kick_notify(struct nouveau_pushbuf *); /* nvc0_draw.c */ extern struct draw_stage *nvc0_draw_render_stage(struct nvc0_context *); /* nvc0_program.c */ -boolean nvc0_program_translate(struct nvc0_program *, uint16_t chipset); -boolean nvc0_program_upload_code(struct nvc0_context *, struct nvc0_program *); +bool nvc0_program_translate(struct nvc0_program *, uint16_t chipset); +bool nvc0_program_upload_code(struct nvc0_context *, struct nvc0_program *); void nvc0_program_destroy(struct nvc0_context *, struct nvc0_program *); void nvc0_program_library_upload(struct nvc0_context *); uint32_t nvc0_program_symbol_offset(const struct nvc0_program *, @@ -231,7 +235,7 @@ void nvc0_query_pushbuf_submit(struct nouveau_pushbuf *, void nvc0_query_fifo_wait(struct nouveau_pushbuf *, struct pipe_query *); void nvc0_so_target_save_offset(struct pipe_context *, struct pipe_stream_output_target *, unsigned i, - boolean *serialize); + bool *serialize); #define NVC0_QUERY_TFB_BUFFER_OFFSET (PIPE_QUERY_TYPES + 0) @@ -250,8 +254,8 @@ extern void nvc0_init_state_functions(struct nvc0_context *); /* nvc0_state_validate.c */ void nvc0_validate_global_residents(struct nvc0_context *, struct nouveau_bufctx *, int bin); -extern boolean nvc0_state_validate(struct nvc0_context *, uint32_t state_mask, - unsigned space_words); +extern bool nvc0_state_validate(struct nvc0_context *, uint32_t state_mask, + unsigned space_words); /* nvc0_surface.c */ extern void nvc0_clear(struct pipe_context *, unsigned buffers, @@ -260,7 +264,7 @@ extern void nvc0_clear(struct pipe_context *, unsigned buffers, extern void nvc0_init_surface_functions(struct nvc0_context *); /* nvc0_tex.c */ -boolean nve4_validate_tsc(struct nvc0_context *nvc0, int s); +bool nve4_validate_tsc(struct nvc0_context *nvc0, int s); void nvc0_validate_textures(struct nvc0_context *); void nvc0_validate_samplers(struct nvc0_context *); void nve4_set_tex_handles(struct nvc0_context *); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c index 3875bbf4ca4..15991c3d2bd 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c @@ -29,13 +29,13 @@ #include "nvc0/nvc0_resource.h" static uint32_t -nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz, boolean is_3d) +nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz, bool is_3d) { return nv50_tex_choose_tile_dims_helper(nx, ny, nz, is_3d); } static uint32_t -nvc0_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) +nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed) { const unsigned ms = util_logbase2(mt->base.base.nr_samples); @@ -133,7 +133,7 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) return tile_flags; } -static INLINE boolean +static inline bool nvc0_miptree_init_ms_mode(struct nv50_miptree *mt) { switch (mt->base.base.nr_samples) { @@ -157,9 +157,9 @@ nvc0_miptree_init_ms_mode(struct nv50_miptree *mt) break; default: NOUVEAU_ERR("invalid nr_samples: %u\n", mt->base.base.nr_samples); - return FALSE; + return false; } - return TRUE; + return true; } static void @@ -250,7 +250,7 @@ nvc0_miptree_create(struct pipe_screen *pscreen, struct nouveau_device *dev = nouveau_screen(pscreen)->device; struct nv50_miptree *mt = CALLOC_STRUCT(nv50_miptree); struct pipe_resource *pt = &mt->base.base; - boolean compressed = dev->drm_version >= 0x01000101; + bool compressed = dev->drm_version >= 0x01000101; int ret; union nouveau_bo_config bo_config; uint32_t bo_flags; @@ -325,7 +325,7 @@ nvc0_miptree_create(struct pipe_screen *pscreen, } /* Offset of zslice @z from start of level @l. */ -INLINE unsigned +inline unsigned nvc0_mt_zslice_offset(const struct nv50_miptree *mt, unsigned l, unsigned z) { const struct pipe_resource *pt = &mt->base.base; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c index e1f5a8c4416..507a2507fe3 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c @@ -31,24 +31,25 @@ * 124 scalar varying values. */ static uint32_t -nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase) +nvc0_shader_input_address(unsigned sn, unsigned si) { switch (sn) { - case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4; + case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4; + case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4; + case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10; case TGSI_SEMANTIC_PRIMID: return 0x060; case TGSI_SEMANTIC_LAYER: return 0x064; case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068; case TGSI_SEMANTIC_PSIZE: return 0x06c; case TGSI_SEMANTIC_POSITION: return 0x070; - case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10; + case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10; case TGSI_SEMANTIC_FOG: return 0x2e8; case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10; case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10; - case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4; case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10; case TGSI_SEMANTIC_CLIPVERTEX: return 0x270; case TGSI_SEMANTIC_PCOORD: return 0x2e0; - case NV50_SEMANTIC_TESSCOORD: return 0x2f0; + case TGSI_SEMANTIC_TESSCOORD: return 0x2f0; case TGSI_SEMANTIC_INSTANCEID: return 0x2f8; case TGSI_SEMANTIC_VERTEXID: return 0x2fc; case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10; @@ -60,20 +61,21 @@ nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase) } static uint32_t -nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase) +nvc0_shader_output_address(unsigned sn, unsigned si) { switch (sn) { - case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4; + case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4; + case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4; + case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10; case TGSI_SEMANTIC_PRIMID: return 0x060; case TGSI_SEMANTIC_LAYER: return 0x064; case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068; case TGSI_SEMANTIC_PSIZE: return 0x06c; case TGSI_SEMANTIC_POSITION: return 0x070; - case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10; + case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10; case TGSI_SEMANTIC_FOG: return 0x2e8; case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10; case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10; - case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4; case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10; case TGSI_SEMANTIC_CLIPVERTEX: return 0x270; case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10; @@ -95,7 +97,7 @@ nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info) case TGSI_SEMANTIC_VERTEXID: info->in[i].mask = 0x1; info->in[i].slot[0] = - nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4; + nvc0_shader_input_address(info->in[i].sn, 0) / 4; continue; default: break; @@ -111,18 +113,11 @@ nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info) static int nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info) { - unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10); unsigned offset; unsigned i, c; for (i = 0; i < info->numInputs; ++i) { - offset = nvc0_shader_input_address(info->in[i].sn, - info->in[i].si, ubase); - if (info->in[i].patch && offset >= 0x20) - offset = 0x20 + info->in[i].si * 0x10; - - if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD) - info->in[i].mask &= 3; + offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si); for (c = 0; c < 4; ++c) info->in[i].slot[c] = (offset + c * 0x4) / 4; @@ -157,15 +152,11 @@ nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info) static int nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info) { - unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10); unsigned offset; unsigned i, c; for (i = 0; i < info->numOutputs; ++i) { - offset = nvc0_shader_output_address(info->out[i].sn, - info->out[i].si, ubase); - if (info->out[i].patch && offset >= 0x20) - offset = 0x20 + info->out[i].si * 0x10; + offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si); for (c = 0; c < 4; ++c) info->out[i].slot[c] = (offset + c * 0x4) / 4; @@ -193,7 +184,7 @@ nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info) return ret; } -static INLINE void +static inline void nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot) { uint8_t min = (vp->hdr[4] >> 12) & 0xff; @@ -216,12 +207,8 @@ nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info) continue; for (c = 0; c < 4; ++c) { a = info->in[i].slot[c]; - if (info->in[i].mask & (1 << c)) { - if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD) - vp->hdr[5 + a / 32] |= 1 << (a % 32); - else - nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]); - } + if (info->in[i].mask & (1 << c)) + vp->hdr[5 + a / 32] |= 1 << (a % 32); } } @@ -250,6 +237,14 @@ nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info) case TGSI_SEMANTIC_VERTEXID: vp->hdr[10] |= 1 << 31; break; + case TGSI_SEMANTIC_TESSCOORD: + /* We don't have the mask, nor the slots populated. While this could + * be achieved, the vast majority of the time if either of the coords + * are read, then both will be read. + */ + nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4); + nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4); + break; default: break; } @@ -277,7 +272,6 @@ nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info) return nvc0_vtgp_gen_header(vp, info); } -#if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN) static void nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info) { @@ -305,14 +299,13 @@ nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info) tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED; switch (info->prop.tp.partitioning) { - case PIPE_TESS_PART_INTEGER: - case PIPE_TESS_PART_POW2: + case PIPE_TESS_SPACING_EQUAL: tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL; break; - case PIPE_TESS_PART_FRACT_ODD: + case PIPE_TESS_SPACING_FRACTIONAL_ODD: tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD; break; - case PIPE_TESS_PART_FRACT_EVEN: + case PIPE_TESS_SPACING_FRACTIONAL_EVEN: tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN; break; default: @@ -320,9 +313,7 @@ nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info) break; } } -#endif -#ifdef PIPE_SHADER_HULL static int nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info) { @@ -346,9 +337,7 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info) return 0; } -#endif -#ifdef PIPE_SHADER_DOMAIN static int nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info) { @@ -365,7 +354,6 @@ nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info) return 0; } -#endif static int nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info) @@ -523,7 +511,7 @@ nvc0_program_dump(struct nvc0_program *prog) } #endif -boolean +bool nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset) { struct nv50_ir_prog_info *info; @@ -531,7 +519,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset) info = CALLOC_STRUCT(nv50_ir_prog_info); if (!info) - return FALSE; + return false; info->type = prog->type; info->target = chipset; @@ -598,16 +586,12 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset) case PIPE_SHADER_VERTEX: ret = nvc0_vp_gen_header(prog, info); break; -#ifdef PIPE_SHADER_HULL - case PIPE_SHADER_HULL: + case PIPE_SHADER_TESS_CTRL: ret = nvc0_tcp_gen_header(prog, info); break; -#endif -#ifdef PIPE_SHADER_DOMAIN - case PIPE_SHADER_DOMAIN: + case PIPE_SHADER_TESS_EVAL: ret = nvc0_tep_gen_header(prog, info); break; -#endif case PIPE_SHADER_GEOMETRY: ret = nvc0_gp_gen_header(prog, info); break; @@ -630,7 +614,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset) assert(info->bin.tlsSpace < (1 << 24)); prog->hdr[0] |= 1 << 26; prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */ - prog->need_tls = TRUE; + prog->need_tls = true; } /* TODO: factor 2 only needed where joinat/precont is used, * and we only have to count non-uniform branches @@ -638,7 +622,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset) /* if ((info->maxCFDepth * 2) > 16) { prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200; - prog->need_tls = TRUE; + prog->need_tls = true; } */ if (info->io.globalAccess) @@ -655,11 +639,11 @@ out: return !ret; } -boolean +bool nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog) { struct nvc0_screen *screen = nvc0->screen; - const boolean is_cp = prog->type == PIPE_SHADER_COMPUTE; + const bool is_cp = prog->type == PIPE_SHADER_COMPUTE; int ret; uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE); uint32_t lib_pos = screen->lib_code->start; @@ -694,7 +678,7 @@ nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog) ret = nouveau_heap_alloc(heap, size, prog, &prog->mem); if (ret) { NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size); - return FALSE; + return false; } IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0); } @@ -729,7 +713,7 @@ nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog) nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0); #ifdef DEBUG - if (debug_get_bool_option("NV50_PROG_DEBUG", FALSE)) + if (debug_get_bool_option("NV50_PROG_DEBUG", false)) nvc0_program_dump(prog); #endif @@ -746,7 +730,7 @@ nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog) BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1); PUSH_DATA (nvc0->base.pushbuf, 0x1011); - return TRUE; + return true; } /* Upload code for builtin functions like integer division emulation. */ diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.h b/src/gallium/drivers/nouveau/nvc0/nvc0_program.h index 3fd9d21b4c4..390e0c7a4f0 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.h @@ -21,8 +21,8 @@ struct nvc0_program { struct pipe_shader_state pipe; ubyte type; - boolean translated; - boolean need_tls; + bool translated; + bool need_tls; uint8_t num_gprs; uint32_t *code; @@ -41,7 +41,7 @@ struct nvc0_program { uint8_t clip_enable; /* mask of defined clip planes */ uint8_t num_ucps; /* also set to max if ClipDistance is used */ uint8_t edgeflag; /* attribute index of edgeflag input */ - boolean need_vertex_id; + bool need_vertex_id; } vp; struct { uint8_t early_z; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c index aea6cbda02d..f7b85a8e931 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c @@ -44,7 +44,7 @@ struct nvc0_query { uint32_t base; uint32_t offset; /* base + i * rotate */ uint8_t state; - boolean is64bit; + bool is64bit; uint8_t rotate; int nesting; /* only used for occlusion queries */ union { @@ -62,13 +62,13 @@ static void nvc0_mp_pm_query_end(struct nvc0_context *, struct nvc0_query *); static boolean nvc0_mp_pm_query_result(struct nvc0_context *, struct nvc0_query *, void *, boolean); -static INLINE struct nvc0_query * +static inline struct nvc0_query * nvc0_query(struct pipe_query *pipe) { return (struct nvc0_query *)pipe; } -static boolean +static bool nvc0_query_allocate(struct nvc0_context *nvc0, struct nvc0_query *q, int size) { struct nvc0_screen *screen = nvc0->screen; @@ -87,17 +87,17 @@ nvc0_query_allocate(struct nvc0_context *nvc0, struct nvc0_query *q, int size) if (size) { q->u.mm = nouveau_mm_allocate(screen->base.mm_GART, size, &q->bo, &q->base); if (!q->bo) - return FALSE; + return false; q->offset = q->base; ret = nouveau_bo_map(q->bo, 0, screen->base.client); if (ret) { nvc0_query_allocate(nvc0, q, 0); - return FALSE; + return false; } q->data = (uint32_t *)((uint8_t *)q->bo->map + q->base); } - return TRUE; + return true; } static void @@ -126,17 +126,17 @@ nvc0_query_create(struct pipe_context *pipe, unsigned type, unsigned index) space = NVC0_QUERY_ALLOC_SPACE; break; case PIPE_QUERY_PIPELINE_STATISTICS: - q->is64bit = TRUE; + q->is64bit = true; space = 512; break; case PIPE_QUERY_SO_STATISTICS: case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - q->is64bit = TRUE; + q->is64bit = true; space = 64; break; case PIPE_QUERY_PRIMITIVES_GENERATED: case PIPE_QUERY_PRIMITIVES_EMITTED: - q->is64bit = TRUE; + q->is64bit = true; q->index = index; space = 32; break; @@ -257,11 +257,11 @@ nvc0_query_begin(struct pipe_context *pipe, struct pipe_query *pq) struct nvc0_context *nvc0 = nvc0_context(pipe); struct nouveau_pushbuf *push = nvc0->base.pushbuf; struct nvc0_query *q = nvc0_query(pq); - boolean ret = true; + bool ret = true; /* For occlusion queries we have to change the storage, because a previous - * query might set the initial render conition to FALSE even *after* we re- - * initialized it to TRUE. + * query might set the initial render conition to false even *after* we re- + * initialized it to true. */ if (q->rotate) { nvc0_query_rotate(nvc0, q); @@ -270,7 +270,7 @@ nvc0_query_begin(struct pipe_context *pipe, struct pipe_query *pq) * query ? */ q->data[0] = q->sequence; /* initialize sequence */ - q->data[1] = 1; /* initial render condition = TRUE */ + q->data[1] = 1; /* initial render condition = true */ q->data[4] = q->sequence + 1; /* for comparison COND_MODE */ q->data[5] = 0; } @@ -401,7 +401,7 @@ nvc0_query_end(struct pipe_context *pipe, struct pipe_query *pq) nvc0_query_get(push, q, 0x00, 0x0d005002 | (q->index << 5)); break; case PIPE_QUERY_TIMESTAMP_DISJOINT: - /* This query is not issued on GPU because disjoint is forced to FALSE */ + /* This query is not issued on GPU because disjoint is forced to false */ q->state = NVC0_QUERY_STATE_READY; break; default: @@ -422,7 +422,7 @@ nvc0_query_end(struct pipe_context *pipe, struct pipe_query *pq) nouveau_fence_ref(nvc0->screen->base.fence.current, &q->fence); } -static INLINE void +static inline void nvc0_query_update(struct nouveau_client *cli, struct nvc0_query *q) { if (q->is64bit) { @@ -442,7 +442,7 @@ nvc0_query_result(struct pipe_context *pipe, struct pipe_query *pq, struct nvc0_query *q = nvc0_query(pq); uint64_t *res64 = (uint64_t*)result; uint32_t *res32 = (uint32_t*)result; - boolean *res8 = (boolean*)result; + uint8_t *res8 = (uint8_t*)result; uint64_t *data64 = (uint64_t *)q->data; unsigned i; @@ -450,7 +450,7 @@ nvc0_query_result(struct pipe_context *pipe, struct pipe_query *pq, if (q->type >= NVC0_QUERY_DRV_STAT(0) && q->type <= NVC0_QUERY_DRV_STAT_LAST) { res64[0] = q->u.value; - return TRUE; + return true; } else #endif if ((q->type >= NVE4_PM_QUERY(0) && q->type <= NVE4_PM_QUERY_LAST) || @@ -468,17 +468,17 @@ nvc0_query_result(struct pipe_context *pipe, struct pipe_query *pq, /* flush for silly apps that spin on GL_QUERY_RESULT_AVAILABLE */ PUSH_KICK(nvc0->base.pushbuf); } - return FALSE; + return false; } if (nouveau_bo_wait(q->bo, NOUVEAU_BO_RD, nvc0->screen->base.client)) - return FALSE; + return false; NOUVEAU_DRV_STAT(&nvc0->screen->base, query_sync_count, 1); } q->state = NVC0_QUERY_STATE_READY; switch (q->type) { case PIPE_QUERY_GPU_FINISHED: - res8[0] = TRUE; + res8[0] = true; break; case PIPE_QUERY_OCCLUSION_COUNTER: /* u32 sequence, u32 count, u64 time */ res64[0] = q->data[1] - q->data[5]; @@ -502,7 +502,7 @@ nvc0_query_result(struct pipe_context *pipe, struct pipe_query *pq, break; case PIPE_QUERY_TIMESTAMP_DISJOINT: res64[0] = 1000000000; - res8[8] = FALSE; + res8[8] = false; break; case PIPE_QUERY_TIME_ELAPSED: res64[0] = data64[1] - data64[3]; @@ -516,10 +516,10 @@ nvc0_query_result(struct pipe_context *pipe, struct pipe_query *pq, break; default: assert(0); /* can't happen, we don't create queries with invalid type */ - return FALSE; + return false; } - return TRUE; + return true; } void @@ -549,7 +549,7 @@ nvc0_render_condition(struct pipe_context *pipe, struct nouveau_pushbuf *push = nvc0->base.pushbuf; struct nvc0_query *q; uint32_t cond; - boolean wait = + bool wait = mode != PIPE_RENDER_COND_NO_WAIT && mode != PIPE_RENDER_COND_BY_REGION_NO_WAIT; @@ -563,7 +563,7 @@ nvc0_render_condition(struct pipe_context *pipe, case PIPE_QUERY_SO_OVERFLOW_PREDICATE: cond = condition ? NVC0_3D_COND_MODE_EQUAL : NVC0_3D_COND_MODE_NOT_EQUAL; - wait = TRUE; + wait = true; break; case PIPE_QUERY_OCCLUSION_COUNTER: case PIPE_QUERY_OCCLUSION_PREDICATE: @@ -626,12 +626,12 @@ nvc0_query_pushbuf_submit(struct nouveau_pushbuf *push, void nvc0_so_target_save_offset(struct pipe_context *pipe, struct pipe_stream_output_target *ptarg, - unsigned index, boolean *serialize) + unsigned index, bool *serialize) { struct nvc0_so_target *targ = nvc0_so_target(ptarg); if (*serialize) { - *serialize = FALSE; + *serialize = false; PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1); IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0); @@ -1080,7 +1080,7 @@ nvc0_mp_pm_query_begin(struct nvc0_context *nvc0, struct nvc0_query *q) { struct nvc0_screen *screen = nvc0->screen; struct nouveau_pushbuf *push = nvc0->base.pushbuf; - const boolean is_nve4 = screen->base.class_3d >= NVE4_3D_CLASS; + const bool is_nve4 = screen->base.class_3d >= NVE4_3D_CLASS; const struct nvc0_mp_pm_query_cfg *cfg; unsigned i, c; unsigned num_ab[2] = { 0, 0 }; @@ -1101,7 +1101,7 @@ nvc0_mp_pm_query_begin(struct nvc0_context *nvc0, struct nvc0_query *q) PUSH_SPACE(push, 4 * 8 * (is_nve4 ? 1 : 6) + 6); if (!screen->pm.mp_counters_enabled) { - screen->pm.mp_counters_enabled = TRUE; + screen->pm.mp_counters_enabled = true; BEGIN_NVC0(push, SUBC_SW(0x06ac), 1); PUSH_DATA (push, 0x1fcb); } @@ -1168,7 +1168,7 @@ nvc0_mp_pm_query_end(struct nvc0_context *nvc0, struct nvc0_query *q) struct nvc0_screen *screen = nvc0->screen; struct pipe_context *pipe = &nvc0->base.pipe; struct nouveau_pushbuf *push = nvc0->base.pushbuf; - const boolean is_nve4 = screen->base.class_3d >= NVE4_3D_CLASS; + const bool is_nve4 = screen->base.class_3d >= NVE4_3D_CLASS; uint32_t mask; uint32_t input[3]; const uint block[3] = { 32, is_nve4 ? 4 : 1, 1 }; @@ -1181,7 +1181,7 @@ nvc0_mp_pm_query_end(struct nvc0_context *nvc0, struct nvc0_query *q) if (unlikely(!screen->pm.prog)) { struct nvc0_program *prog = CALLOC_STRUCT(nvc0_program); prog->type = PIPE_SHADER_COMPUTE; - prog->translated = TRUE; + prog->translated = true; prog->num_gprs = 14; prog->parm_size = 12; if (is_nve4) { @@ -1249,9 +1249,9 @@ nvc0_mp_pm_query_end(struct nvc0_context *nvc0, struct nvc0_query *q) } } -static INLINE boolean +static inline bool nvc0_mp_pm_query_read_data(uint32_t count[32][4], - struct nvc0_context *nvc0, boolean wait, + struct nvc0_context *nvc0, bool wait, struct nvc0_query *q, const struct nvc0_mp_pm_query_cfg *cfg, unsigned mp_count) @@ -1264,19 +1264,19 @@ nvc0_mp_pm_query_read_data(uint32_t count[32][4], for (c = 0; c < cfg->num_counters; ++c) { if (q->data[b + 8] != q->sequence) { if (!wait) - return FALSE; + return false; if (nouveau_bo_wait(q->bo, NOUVEAU_BO_RD, nvc0->base.client)) - return FALSE; + return false; } count[p][c] = q->data[b + q->ctr[c]]; } } - return TRUE; + return true; } -static INLINE boolean +static inline bool nve4_mp_pm_query_read_data(uint32_t count[32][4], - struct nvc0_context *nvc0, boolean wait, + struct nvc0_context *nvc0, bool wait, struct nvc0_query *q, const struct nvc0_mp_pm_query_cfg *cfg, unsigned mp_count) @@ -1291,9 +1291,9 @@ nve4_mp_pm_query_read_data(uint32_t count[32][4], for (d = 0; d < ((q->ctr[c] & ~3) ? 1 : 4); ++d) { if (q->data[b + 20 + d] != q->sequence) { if (!wait) - return FALSE; + return false; if (nouveau_bo_wait(q->bo, NOUVEAU_BO_RD, nvc0->base.client)) - return FALSE; + return false; } if (q->ctr[c] & ~0x3) count[p][c] = q->data[b + 16 + (q->ctr[c] & 3)]; @@ -1302,7 +1302,7 @@ nve4_mp_pm_query_read_data(uint32_t count[32][4], } } } - return TRUE; + return true; } /* Metric calculations: @@ -1325,7 +1325,7 @@ nvc0_mp_pm_query_result(struct nvc0_context *nvc0, struct nvc0_query *q, unsigned mp_count = MIN2(nvc0->screen->mp_count_compute, 32); unsigned p, c; const struct nvc0_mp_pm_query_cfg *cfg; - boolean ret; + bool ret; cfg = nvc0_mp_pm_query_get_cfg(nvc0, q); @@ -1334,7 +1334,7 @@ nvc0_mp_pm_query_result(struct nvc0_context *nvc0, struct nvc0_query *q, else ret = nvc0_mp_pm_query_read_data(count, nvc0, wait, q, cfg, mp_count); if (!ret) - return FALSE; + return false; if (cfg->op == NVC0_COUNTER_OPn_SUM) { for (c = 0; c < cfg->num_counters; ++c) @@ -1394,7 +1394,7 @@ nvc0_mp_pm_query_result(struct nvc0_context *nvc0, struct nvc0_query *q, } *(uint64_t *)result = value; - return TRUE; + return true; } int diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 56c230e42fc..ab19b26f156 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -44,16 +44,16 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen, unsigned bindings) { if (sample_count > 8) - return FALSE; + return false; if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ - return FALSE; + return false; if (!util_format_is_supported(format, bindings)) - return FALSE; + return false; if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER)) if (util_format_get_blocksizebits(format) == 3 * 32) - return FALSE; + return false; /* transfers & shared are always supported */ bindings &= ~(PIPE_BIND_TRANSFER_READ | @@ -120,6 +120,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50; case PIPE_CAP_ENDIANNESS: return PIPE_ENDIAN_LITTLE; + case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: + return 30; /* supported caps */ case PIPE_CAP_TEXTURE_MIRROR_CLAMP: @@ -163,7 +165,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_USER_CONSTANT_BUFFERS: case PIPE_CAP_USER_INDEX_BUFFERS: case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_SAMPLE_SHADING: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: @@ -174,11 +175,16 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CLIP_HALFZ: case PIPE_CAP_POLYGON_OFFSET_CLAMP: case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: + case PIPE_CAP_TEXTURE_FLOAT_LINEAR: + case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: + case PIPE_CAP_DEPTH_BOUNDS_TEST: return 1; case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: return (class_3d >= NVE4_3D_CLASS) ? 1 : 0; case PIPE_CAP_COMPUTE: return (class_3d == NVE4_3D_CLASS) ? 1 : 0; + case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: + return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0; /* unsupported caps */ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: @@ -226,13 +232,14 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, switch (shader) { case PIPE_SHADER_VERTEX: - /* - case PIPE_SHADER_TESSELLATION_CONTROL: - case PIPE_SHADER_TESSELLATION_EVALUATION: - */ case PIPE_SHADER_GEOMETRY: case PIPE_SHADER_FRAGMENT: break; + case PIPE_SHADER_TESS_CTRL: + case PIPE_SHADER_TESS_EVAL: + if (class_3d >= GM107_3D_CLASS) + return 0; + break; case PIPE_SHADER_COMPUTE: if (class_3d != NVE4_3D_CLASS) return 0; @@ -341,6 +348,7 @@ nvc0_screen_get_compute_param(struct pipe_screen *pscreen, enum pipe_compute_cap param, void *data) { uint64_t *data64 = (uint64_t *)data; + uint32_t *data32 = (uint32_t *)data; const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass; switch (param) { @@ -372,6 +380,9 @@ nvc0_screen_get_compute_param(struct pipe_screen *pscreen, case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */ data64[0] = 4096; return 8; + case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: + data32[0] = 32; + return 4; default: return 0; } @@ -550,7 +561,7 @@ nvc0_screen_init_compute(struct nvc0_screen *screen) /* Using COMPUTE has weird effects on 3D state, we need to * investigate this further before enabling it by default. */ - if (debug_get_bool_option("NVC0_COMPUTE", FALSE)) + if (debug_get_bool_option("NVC0_COMPUTE", false)) return nvc0_screen_compute_setup(screen, screen->base.pushbuf); return 0; case 0xe0: @@ -564,7 +575,7 @@ nvc0_screen_init_compute(struct nvc0_screen *screen) } } -boolean +bool nvc0_screen_resize_tls_area(struct nvc0_screen *screen, uint32_t lpos, uint32_t lneg, uint32_t cstack) { @@ -574,7 +585,7 @@ nvc0_screen_resize_tls_area(struct nvc0_screen *screen, if (size >= (1 << 20)) { NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size); - return FALSE; + return false; } size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */ @@ -587,11 +598,11 @@ nvc0_screen_resize_tls_area(struct nvc0_screen *screen, NULL, &bo); if (ret) { NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size); - return FALSE; + return false; } nouveau_bo_ref(NULL, &screen->tls); screen->tls = bo; - return TRUE; + return true; } #define FAIL_SCREEN_INIT(str, err) \ @@ -610,6 +621,7 @@ nvc0_screen_create(struct nouveau_device *dev) struct nouveau_pushbuf *push; uint64_t value; uint32_t obj_class; + uint32_t flags; int ret; unsigned i; @@ -665,8 +677,11 @@ nvc0_screen_create(struct nouveau_device *dev) screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param; screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported; - ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL, - &screen->fence.bo); + flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP; + if (dev->drm_version >= 0x01000202) + flags |= NOUVEAU_BO_COHERENT; + + ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo); if (ret) goto fail; nouveau_bo_map(screen->fence.bo, 0, NULL); @@ -781,7 +796,7 @@ nvc0_screen_create(struct nouveau_device *dev) BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1); PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS); - if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { + if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) { /* kill shaders after about 1 second (at 100 MHz) */ BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1); PUSH_DATA (push, 0x17); @@ -1012,6 +1027,7 @@ nvc0_screen_create(struct nouveau_device *dev) PUSH_DATA (push, 0x20); BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1); PUSH_DATA (push, 0x00); + screen->save_state.patch_vertices = 3; BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1); PUSH_DATA (push, 0); @@ -1031,7 +1047,7 @@ nvc0_screen_create(struct nouveau_device *dev) if (!nvc0_blitter_create(screen)) goto fail; - nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); + nouveau_fence_new(&screen->base, &screen->base.fence.current, false); return pscreen; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h index ef2bd43f006..d8826ae0c0d 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h @@ -28,16 +28,17 @@ struct nvc0_context; struct nvc0_blitter; struct nvc0_graph_state { - boolean flushed; - boolean rasterizer_discard; - boolean early_z_forced; - boolean prim_restart; + bool flushed; + bool rasterizer_discard; + bool early_z_forced; + bool prim_restart; uint32_t instance_elts; /* bitmask of per-instance elements */ uint32_t instance_base; uint32_t constant_vbos; uint32_t constant_elts; int32_t index_bias; uint16_t scissor; + uint8_t patch_vertices; uint8_t vbo_mode; /* 0 = normal, 1 = translate, 3 = translate, forced */ uint8_t num_vtxbufs; uint8_t num_vtxelts; @@ -95,7 +96,7 @@ struct nvc0_screen { struct nvc0_program *prog; /* compute state object to read MP counters */ struct pipe_query *mp_counter[8]; /* counter to query allocation */ uint8_t num_mp_pm_active[2]; - boolean mp_counters_enabled; + bool mp_counters_enabled; } pm; struct nouveau_object *eng3d; /* sqrt(1/2)|kepler> + sqrt(1/2)|fermi> */ @@ -105,7 +106,7 @@ struct nvc0_screen { struct nouveau_object *nvsw; }; -static INLINE struct nvc0_screen * +static inline struct nvc0_screen * nvc0_screen(struct pipe_screen *screen) { return (struct nvc0_screen *)screen; @@ -276,7 +277,7 @@ int nvc0_screen_get_driver_query_info(struct pipe_screen *, unsigned, int nvc0_screen_get_driver_query_group_info(struct pipe_screen *, unsigned, struct pipe_driver_query_group_info *); -boolean nvc0_blitter_create(struct nvc0_screen *); +bool nvc0_blitter_create(struct nvc0_screen *); void nvc0_blitter_destroy(struct nvc0_screen *); void nvc0_screen_make_buffers_resident(struct nvc0_screen *); @@ -287,10 +288,10 @@ int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *); int nve4_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *); int nvc0_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *); -boolean nvc0_screen_resize_tls_area(struct nvc0_screen *, uint32_t lpos, - uint32_t lneg, uint32_t cstack); +bool nvc0_screen_resize_tls_area(struct nvc0_screen *, uint32_t lpos, + uint32_t lneg, uint32_t cstack); -static INLINE void +static inline void nvc0_resource_fence(struct nv04_resource *res, uint32_t flags) { struct nvc0_screen *screen = nvc0_screen(res->base.screen); @@ -302,7 +303,7 @@ nvc0_resource_fence(struct nv04_resource *res, uint32_t flags) } } -static INLINE void +static inline void nvc0_resource_validate(struct nv04_resource *res, uint32_t flags) { if (likely(res->bo)) { @@ -325,21 +326,21 @@ struct nvc0_format { extern const struct nvc0_format nvc0_format_table[]; -static INLINE void +static inline void nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic) { if (tic->id >= 0) screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32)); } -static INLINE void +static inline void nvc0_screen_tsc_unlock(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc) { if (tsc->id >= 0) screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32)); } -static INLINE void +static inline void nvc0_screen_tic_free(struct nvc0_screen *screen, struct nv50_tic_entry *tic) { if (tic->id >= 0) { @@ -348,7 +349,7 @@ nvc0_screen_tic_free(struct nvc0_screen *screen, struct nv50_tic_entry *tic) } } -static INLINE void +static inline void nvc0_screen_tsc_free(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc) { if (tsc->id >= 0) { diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c index e0842784a88..8aa127adc0a 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c @@ -27,7 +27,7 @@ #include "nvc0/nvc0_context.h" -static INLINE void +static inline void nvc0_program_update_context_state(struct nvc0_context *nvc0, struct nvc0_program *prog, int stage) { @@ -63,22 +63,22 @@ nvc0_program_update_context_state(struct nvc0_context *nvc0, } } -static INLINE boolean +static inline bool nvc0_program_validate(struct nvc0_context *nvc0, struct nvc0_program *prog) { if (prog->mem) - return TRUE; + return true; if (!prog->translated) { prog->translated = nvc0_program_translate( prog, nvc0->screen->base.device->chipset); if (!prog->translated) - return FALSE; + return false; } if (likely(prog->code_size)) return nvc0_program_upload_code(nvc0, prog); - return TRUE; /* stream output info only */ + return true; /* stream output info only */ } void @@ -147,9 +147,6 @@ nvc0_tctlprog_validate(struct nvc0_context *nvc0) PUSH_DATA (push, tp->code_base); BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(2)), 1); PUSH_DATA (push, tp->num_gprs); - - if (tp->tp.input_patch_size <= 32) - IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), tp->tp.input_patch_size); } else { BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1); PUSH_DATA (push, 0x20); @@ -192,7 +189,7 @@ nvc0_gmtyprog_validate(struct nvc0_context *nvc0) /* we allow GPs with no code for specifying stream output state only */ if (gp && gp->code_size) { - const boolean gp_selects_layer = !!(gp->hdr[13] & (1 << 9)); + const bool gp_selects_layer = !!(gp->hdr[13] & (1 << 9)); BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1); PUSH_DATA (push, 0x41); @@ -280,7 +277,7 @@ nvc0_tfb_validate(struct nvc0_context *nvc0) nvc0_query_pushbuf_submit(push, targ->pq, 0x4); } else { PUSH_DATA(push, 0); /* TFB_BUFFER_OFFSET */ - targ->clean = FALSE; + targ->clean = false; } } for (; b < 4; ++b) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c index 6b7a211e71b..2a33857d9df 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c @@ -35,7 +35,7 @@ #include "nouveau_gldefs.h" -static INLINE uint32_t +static inline uint32_t nvc0_colormask(unsigned mask) { uint32_t ret = 0; @@ -55,7 +55,7 @@ nvc0_colormask(unsigned mask) #define NVC0_BLEND_FACTOR_CASE(a, b) \ case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b -static INLINE uint32_t +static inline uint32_t nvc0_blend_fac(unsigned factor) { switch (factor) { @@ -92,8 +92,8 @@ nvc0_blend_state_create(struct pipe_context *pipe, int r; /* reference */ uint32_t ms; uint8_t blend_en = 0; - boolean indep_masks = FALSE; - boolean indep_funcs = FALSE; + bool indep_masks = false; + bool indep_funcs = false; so->pipe = *cso; @@ -111,7 +111,7 @@ nvc0_blend_state_create(struct pipe_context *pipe, cso->rt[i].alpha_func != cso->rt[r].alpha_func || cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor || cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) { - indep_funcs = TRUE; + indep_funcs = true; break; } } @@ -120,7 +120,7 @@ nvc0_blend_state_create(struct pipe_context *pipe, for (i = 1; i < 8; ++i) { if (cso->rt[i].colormask != cso->rt[0].colormask) { - indep_masks = TRUE; + indep_masks = true; break; } } @@ -351,6 +351,13 @@ nvc0_zsa_state_create(struct pipe_context *pipe, SB_DATA (so, nvgl_comparison_op(cso->depth.func)); } + SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test); + if (cso->depth.bounds_test) { + SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2); + SB_DATA (so, fui(cso->depth.bounds_min)); + SB_DATA (so, fui(cso->depth.bounds_max)); + } + if (cso->stencil[0].enabled) { SB_BEGIN_3D(so, STENCIL_ENABLE, 5); SB_DATA (so, 1); @@ -428,7 +435,7 @@ nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso) FREE(hwcso); } -static INLINE void +static inline void nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s, unsigned nr, void **hwcso) { @@ -508,6 +515,14 @@ nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader, assert(start == 0); nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s); break; + case PIPE_SHADER_TESS_CTRL: + assert(start == 0); + nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s); + break; + case PIPE_SHADER_TESS_EVAL: + assert(start == 0); + nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s); + break; case PIPE_SHADER_GEOMETRY: assert(start == 0); nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s); @@ -537,7 +552,7 @@ nvc0_sampler_view_destroy(struct pipe_context *pipe, FREE(nv50_tic_entry(view)); } -static INLINE void +static inline void nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s, unsigned nr, struct pipe_sampler_view **views) @@ -633,6 +648,12 @@ nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader, case PIPE_SHADER_VERTEX: nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views); break; + case PIPE_SHADER_TESS_CTRL: + nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views); + break; + case PIPE_SHADER_TESS_EVAL: + nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views); + break; case PIPE_SHADER_GEOMETRY: nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views); break; @@ -734,6 +755,38 @@ nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso) } static void * +nvc0_tcp_state_create(struct pipe_context *pipe, + const struct pipe_shader_state *cso) +{ + return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL); +} + +static void +nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso) +{ + struct nvc0_context *nvc0 = nvc0_context(pipe); + + nvc0->tctlprog = hwcso; + nvc0->dirty |= NVC0_NEW_TCTLPROG; +} + +static void * +nvc0_tep_state_create(struct pipe_context *pipe, + const struct pipe_shader_state *cso) +{ + return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL); +} + +static void +nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso) +{ + struct nvc0_context *nvc0 = nvc0_context(pipe); + + nvc0->tevlprog = hwcso; + nvc0->dirty |= NVC0_NEW_TEVLPROG; +} + +static void * nvc0_cp_state_create(struct pipe_context *pipe, const struct pipe_compute_state *cso) { @@ -790,7 +843,7 @@ nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res); - nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? TRUE : FALSE; + nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false; if (nvc0->constbuf[s][i].user) { nvc0->constbuf[s][i].u.data = cb->user_buffer; nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000); @@ -934,6 +987,18 @@ nvc0_set_viewport_states(struct pipe_context *pipe, } static void +nvc0_set_tess_state(struct pipe_context *pipe, + const float default_tess_outer[4], + const float default_tess_inner[2]) +{ + struct nvc0_context *nvc0 = nvc0_context(pipe); + + memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float)); + memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float)); + nvc0->dirty |= NVC0_NEW_TESSFACTOR; +} + +static void nvc0_set_vertex_buffers(struct pipe_context *pipe, unsigned start_slot, unsigned count, const struct pipe_vertex_buffer *vb) @@ -1018,7 +1083,7 @@ nvc0_so_target_create(struct pipe_context *pipe, FREE(targ); return NULL; } - targ->clean = TRUE; + targ->clean = true; targ->pipe.buffer_size = size; targ->pipe.buffer_offset = offset; @@ -1051,13 +1116,13 @@ nvc0_set_transform_feedback_targets(struct pipe_context *pipe, { struct nvc0_context *nvc0 = nvc0_context(pipe); unsigned i; - boolean serialize = TRUE; + bool serialize = true; assert(num_targets <= 4); for (i = 0; i < num_targets; ++i) { - const boolean changed = nvc0->tfbbuf[i] != targets[i]; - const boolean append = (offsets[i] == ((unsigned)-1)); + const bool changed = nvc0->tfbbuf[i] != targets[i]; + const bool append = (offsets[i] == ((unsigned)-1)); if (!changed && append) continue; nvc0->tfbbuf_dirty |= 1 << i; @@ -1066,7 +1131,7 @@ nvc0_set_transform_feedback_targets(struct pipe_context *pipe, nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize); if (targets[i] && !append) - nvc0_so_target(targets[i])->clean = TRUE; + nvc0_so_target(targets[i])->clean = true; pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]); } @@ -1125,16 +1190,18 @@ nvc0_set_compute_resources(struct pipe_context *pipe, } static void -nvc0_set_shader_resources(struct pipe_context *pipe, - unsigned start, unsigned nr, - struct pipe_surface **resources) +nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader, + unsigned start_slot, unsigned count, + struct pipe_image_view **views) { - nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, resources); +#if 0 + nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, views); nvc0_context(pipe)->dirty |= NVC0_NEW_SURFACES; +#endif } -static INLINE void +static inline void nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res) { struct nv04_resource *buf = nv04_resource(res); @@ -1218,12 +1285,18 @@ nvc0_init_state_functions(struct nvc0_context *nvc0) pipe->create_vs_state = nvc0_vp_state_create; pipe->create_fs_state = nvc0_fp_state_create; pipe->create_gs_state = nvc0_gp_state_create; + pipe->create_tcs_state = nvc0_tcp_state_create; + pipe->create_tes_state = nvc0_tep_state_create; pipe->bind_vs_state = nvc0_vp_state_bind; pipe->bind_fs_state = nvc0_fp_state_bind; pipe->bind_gs_state = nvc0_gp_state_bind; + pipe->bind_tcs_state = nvc0_tcp_state_bind; + pipe->bind_tes_state = nvc0_tep_state_bind; pipe->delete_vs_state = nvc0_sp_state_delete; pipe->delete_fs_state = nvc0_sp_state_delete; pipe->delete_gs_state = nvc0_sp_state_delete; + pipe->delete_tcs_state = nvc0_sp_state_delete; + pipe->delete_tes_state = nvc0_sp_state_delete; pipe->create_compute_state = nvc0_cp_state_create; pipe->bind_compute_state = nvc0_cp_state_bind; @@ -1239,6 +1312,7 @@ nvc0_init_state_functions(struct nvc0_context *nvc0) pipe->set_polygon_stipple = nvc0_set_polygon_stipple; pipe->set_scissor_states = nvc0_set_scissor_states; pipe->set_viewport_states = nvc0_set_viewport_states; + pipe->set_tess_state = nvc0_set_tess_state; pipe->create_vertex_elements_state = nvc0_vertex_state_create; pipe->delete_vertex_elements_state = nvc0_vertex_state_delete; @@ -1253,8 +1327,14 @@ nvc0_init_state_functions(struct nvc0_context *nvc0) pipe->set_global_binding = nvc0_set_global_bindings; pipe->set_compute_resources = nvc0_set_compute_resources; - pipe->set_shader_resources = nvc0_set_shader_resources; + pipe->set_shader_images = nvc0_set_shader_images; nvc0->sample_mask = ~0; nvc0->min_samples = 1; + nvc0->default_tess_outer[0] = + nvc0->default_tess_outer[1] = + nvc0->default_tess_outer[2] = + nvc0->default_tess_outer[3] = 1.0; + nvc0->default_tess_inner[0] = + nvc0->default_tess_inner[1] = 1.0; } diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c index c52399ab312..ce1119c284d 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c @@ -55,7 +55,7 @@ nvc0_validate_zcull(struct nvc0_context *nvc0) } #endif -static INLINE void +static inline void nvc0_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i) { BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 6); @@ -74,7 +74,7 @@ nvc0_validate_fb(struct nvc0_context *nvc0) struct pipe_framebuffer_state *fb = &nvc0->framebuffer; unsigned i, ms; unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1; - boolean serialize = FALSE; + bool serialize = false; nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB); @@ -136,7 +136,7 @@ nvc0_validate_fb(struct nvc0_context *nvc0) } if (res->status & NOUVEAU_BUFFER_STATUS_GPU_READING) - serialize = TRUE; + serialize = true; res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING; @@ -168,7 +168,7 @@ nvc0_validate_fb(struct nvc0_context *nvc0) ms_mode = mt->ms_mode; if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) - serialize = TRUE; + serialize = true; mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING; @@ -309,7 +309,7 @@ nvc0_validate_viewport(struct nvc0_context *nvc0) nvc0->viewports_dirty = 0; } -static INLINE void +static inline void nvc0_upload_uclip_planes(struct nvc0_context *nvc0, unsigned s) { struct nouveau_pushbuf *push = nvc0->base.pushbuf; @@ -324,7 +324,7 @@ nvc0_upload_uclip_planes(struct nvc0_context *nvc0, unsigned s) PUSH_DATAp(push, &nvc0->clip.ucp[0][0], PIPE_MAX_CLIP_PLANES * 4); } -static INLINE void +static inline void nvc0_check_program_ucps(struct nvc0_context *nvc0, struct nvc0_program *vp, uint8_t mask) { @@ -339,7 +339,7 @@ nvc0_check_program_ucps(struct nvc0_context *nvc0, nvc0_vertprog_validate(nvc0); else if (likely(vp == nvc0->gmtyprog)) - nvc0_vertprog_validate(nvc0); + nvc0_gmtyprog_validate(nvc0); else nvc0_tevlprog_validate(nvc0); } @@ -455,6 +455,8 @@ nvc0_constbufs_validate(struct nvc0_context *nvc0) PUSH_DATA (push, (i << 4) | 1); BCTX_REFN(nvc0->bufctx_3d, CB(s, i), res, RD); + + nvc0->cb_dirty = 1; /* Force cache flush for UBO. */ } else { BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1); PUSH_DATA (push, (i << 4) | 0); @@ -518,12 +520,12 @@ static void nvc0_validate_derived_1(struct nvc0_context *nvc0) { struct nouveau_pushbuf *push = nvc0->base.pushbuf; - boolean rasterizer_discard; + bool rasterizer_discard; if (nvc0->rast && nvc0->rast->pipe.rasterizer_discard) { - rasterizer_discard = TRUE; + rasterizer_discard = true; } else { - boolean zs = nvc0->zsa && + bool zs = nvc0->zsa && (nvc0->zsa->pipe.depth.enabled || nvc0->zsa->pipe.stencil[0].enabled); rasterizer_discard = !zs && (!nvc0->fragprog || !nvc0->fragprog->hdr[18]); @@ -535,6 +537,33 @@ nvc0_validate_derived_1(struct nvc0_context *nvc0) } } +/* alpha test is disabled if there are no color RTs, so make sure we have at + * least one if alpha test is enabled. Note that this must run after + * nvc0_validate_fb, otherwise that will override the RT count setting. + */ +static void +nvc0_validate_derived_2(struct nvc0_context *nvc0) +{ + struct nouveau_pushbuf *push = nvc0->base.pushbuf; + + if (nvc0->zsa && nvc0->zsa->pipe.alpha.enabled && + nvc0->framebuffer.nr_cbufs == 0) { + nvc0_fb_set_null_rt(push, 0); + BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1); + PUSH_DATA (push, (076543210 << 4) | 1); + } +} + +static void +nvc0_validate_tess_state(struct nvc0_context *nvc0) +{ + struct nouveau_pushbuf *push = nvc0->base.pushbuf; + + BEGIN_NVC0(push, NVC0_3D(TESS_LEVEL_OUTER(0)), 6); + PUSH_DATAp(push, nvc0->default_tess_outer, 4); + PUSH_DATAp(push, nvc0->default_tess_inner, 2); +} + static void nvc0_switch_pipe_context(struct nvc0_context *ctx_to) { @@ -593,10 +622,12 @@ static struct state_validate { { nvc0_vertprog_validate, NVC0_NEW_VERTPROG }, { nvc0_tctlprog_validate, NVC0_NEW_TCTLPROG }, { nvc0_tevlprog_validate, NVC0_NEW_TEVLPROG }, + { nvc0_validate_tess_state, NVC0_NEW_TESSFACTOR }, { nvc0_gmtyprog_validate, NVC0_NEW_GMTYPROG }, { nvc0_fragprog_validate, NVC0_NEW_FRAGPROG }, { nvc0_validate_derived_1, NVC0_NEW_FRAGPROG | NVC0_NEW_ZSA | NVC0_NEW_RASTERIZER }, + { nvc0_validate_derived_2, NVC0_NEW_ZSA | NVC0_NEW_FRAMEBUFFER }, { nvc0_validate_clip, NVC0_NEW_CLIP | NVC0_NEW_RASTERIZER | NVC0_NEW_VERTPROG | NVC0_NEW_TEVLPROG | @@ -613,7 +644,7 @@ static struct state_validate { }; #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0])) -boolean +bool nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask, unsigned words) { uint32_t state_mask; @@ -634,15 +665,15 @@ nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask, unsigned words) } nvc0->dirty &= ~state_mask; - nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, FALSE); + nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, false); } nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_3d); ret = nouveau_pushbuf_validate(nvc0->base.pushbuf); if (unlikely(nvc0->state.flushed)) { - nvc0->state.flushed = FALSE; - nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, TRUE); + nvc0->state.flushed = false; + nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, true); } return !ret; } diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h b/src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h index 1d70b7c7b23..18fcc12dea3 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h @@ -29,7 +29,7 @@ struct nvc0_rasterizer_stateobj { struct nvc0_zsa_stateobj { struct pipe_depth_stencil_alpha_state pipe; int size; - uint32_t state[26]; + uint32_t state[30]; }; struct nvc0_constbuf { @@ -39,7 +39,7 @@ struct nvc0_constbuf { } u; uint32_t size; uint32_t offset; - boolean user; /* should only be TRUE if u.data is valid and non-NULL */ + bool user; /* should only be true if u.data is valid and non-NULL */ }; struct nvc0_vertex_element { @@ -55,8 +55,8 @@ struct nvc0_vertex_stateobj { unsigned num_elements; uint32_t instance_elts; uint32_t instance_bufs; - boolean shared_slots; - boolean need_conversion; /* e.g. VFETCH cannot convert f64 to f32 */ + bool shared_slots; + bool need_conversion; /* e.g. VFETCH cannot convert f64 to f32 */ unsigned size; /* size of vertex in bytes (when packed) */ struct nvc0_vertex_element element[0]; }; @@ -65,10 +65,10 @@ struct nvc0_so_target { struct pipe_stream_output_target pipe; struct pipe_query *pq; unsigned stride; - boolean clean; + bool clean; }; -static INLINE struct nvc0_so_target * +static inline struct nvc0_so_target * nvc0_so_target(struct pipe_stream_output_target *ptarg) { return (struct nvc0_so_target *)ptarg; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c index a820de7259a..51a6f93f891 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c @@ -47,8 +47,8 @@ #define NOUVEAU_DRIVER 0xc0 #include "nv50/nv50_blit.h" -static INLINE uint8_t -nvc0_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal) +static inline uint8_t +nvc0_2d_format(enum pipe_format format, bool dst, bool dst_src_equal) { uint8_t id = nvc0_format_table[format].rt; @@ -81,9 +81,9 @@ nvc0_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal) } static int -nvc0_2d_texture_set(struct nouveau_pushbuf *push, boolean dst, +nvc0_2d_texture_set(struct nouveau_pushbuf *push, bool dst, struct nv50_miptree *mt, unsigned level, unsigned layer, - enum pipe_format pformat, boolean dst_src_pformat_equal) + enum pipe_format pformat, bool dst_src_pformat_equal) { struct nouveau_bo *bo = mt->base.bo; uint32_t width, height, depth; @@ -161,16 +161,16 @@ nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push, const enum pipe_format dfmt = dst->base.base.format; const enum pipe_format sfmt = src->base.base.format; int ret; - boolean eqfmt = dfmt == sfmt; + bool eqfmt = dfmt == sfmt; if (!PUSH_SPACE(push, 2 * 16 + 32)) return PIPE_ERROR; - ret = nvc0_2d_texture_set(push, TRUE, dst, dst_level, dz, dfmt, eqfmt); + ret = nvc0_2d_texture_set(push, true, dst, dst_level, dz, dfmt, eqfmt); if (ret) return ret; - ret = nvc0_2d_texture_set(push, FALSE, src, src_level, sz, sfmt, eqfmt); + ret = nvc0_2d_texture_set(push, false, src, src_level, sz, sfmt, eqfmt); if (ret) return ret; @@ -189,7 +189,7 @@ nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push, PUSH_DATA (push, 0); PUSH_DATA (push, sx << src->ms_x); PUSH_DATA (push, 0); - PUSH_DATA (push, sy << src->ms_x); + PUSH_DATA (push, sy << src->ms_y); return 0; } @@ -203,7 +203,7 @@ nvc0_resource_copy_region(struct pipe_context *pipe, { struct nvc0_context *nvc0 = nvc0_context(pipe); int ret; - boolean m2mf; + bool m2mf; unsigned dst_layer = dstz, src_layer = src_box->z; if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { @@ -704,7 +704,7 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit) }; blit->vp.type = PIPE_SHADER_VERTEX; - blit->vp.translated = TRUE; + blit->vp.translated = true; if (blit->screen->base.class_3d >= GM107_3D_CLASS) { blit->vp.code = (uint32_t *)code_gm107; /* const_cast */ blit->vp.code_size = sizeof(code_gm107); @@ -1217,7 +1217,7 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info) int i; uint32_t mode; uint32_t mask = nv50_blit_eng2d_get_mask(info); - boolean b; + bool b; mode = nv50_blit_get_filter(info) ? NV50_2D_BLIT_CONTROL_FILTER_BILINEAR : @@ -1376,39 +1376,40 @@ static void nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info) { struct nvc0_context *nvc0 = nvc0_context(pipe); - boolean eng3d = FALSE; + struct nouveau_pushbuf *push = nvc0->base.pushbuf; + bool eng3d = false; if (util_format_is_depth_or_stencil(info->dst.resource->format)) { if (!(info->mask & PIPE_MASK_ZS)) return; if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT || info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) - eng3d = TRUE; + eng3d = true; if (info->filter != PIPE_TEX_FILTER_NEAREST) - eng3d = TRUE; + eng3d = true; } else { if (!(info->mask & PIPE_MASK_RGBA)) return; if (info->mask != PIPE_MASK_RGBA) - eng3d = TRUE; + eng3d = true; } if (nv50_miptree(info->src.resource)->layout_3d) { - eng3d = TRUE; + eng3d = true; } else if (info->src.box.depth != info->dst.box.depth) { - eng3d = TRUE; + eng3d = true; debug_printf("blit: cannot filter array or cube textures in z direction"); } if (!eng3d && info->dst.format != info->src.format) { if (!nv50_2d_dst_format_faithful(info->dst.format)) { - eng3d = TRUE; + eng3d = true; } else if (!nv50_2d_src_format_faithful(info->src.format)) { if (!util_format_is_luminance(info->src.format)) { if (!nv50_2d_dst_format_ops_supported(info->dst.format)) - eng3d = TRUE; + eng3d = true; else if (util_format_is_intensity(info->src.format)) eng3d = info->src.format != PIPE_FORMAT_I8_UNORM; @@ -1420,30 +1421,36 @@ nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info) } } else if (util_format_is_luminance_alpha(info->src.format)) - eng3d = TRUE; + eng3d = true; } if (info->src.resource->nr_samples == 8 && info->dst.resource->nr_samples <= 1) - eng3d = TRUE; + eng3d = true; #if 0 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */ if (info->src.resource->nr_samples > 1 || info->dst.resource->nr_samples > 1) - eng3d = TRUE; + eng3d = true; #endif /* FIXME: find correct src coordinates adjustments */ if ((info->src.box.width != info->dst.box.width && info->src.box.width != -info->dst.box.width) || (info->src.box.height != info->dst.box.height && info->src.box.height != -info->dst.box.height)) - eng3d = TRUE; + eng3d = true; + + if (nvc0->screen->num_occlusion_queries_active) + IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 0); if (!eng3d) nvc0_blit_eng2d(nvc0, info); else nvc0_blit_3d(nvc0, info); + if (nvc0->screen->num_occlusion_queries_active) + IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1); + NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_blit_count, 1); } @@ -1453,13 +1460,13 @@ nvc0_flush_resource(struct pipe_context *ctx, { } -boolean +bool nvc0_blitter_create(struct nvc0_screen *screen) { screen->blitter = CALLOC_STRUCT(nvc0_blitter); if (!screen->blitter) { NOUVEAU_ERR("failed to allocate blitter struct\n"); - return FALSE; + return false; } screen->blitter->screen = screen; @@ -1468,7 +1475,7 @@ nvc0_blitter_create(struct nvc0_screen *screen) nvc0_blitter_make_vp(screen->blitter); nvc0_blitter_make_sampler(screen->blitter); - return TRUE; + return true; } void @@ -1491,20 +1498,20 @@ nvc0_blitter_destroy(struct nvc0_screen *screen) FREE(blitter); } -boolean +bool nvc0_blitctx_create(struct nvc0_context *nvc0) { nvc0->blit = CALLOC_STRUCT(nvc0_blitctx); if (!nvc0->blit) { NOUVEAU_ERR("failed to allocate blit context\n"); - return FALSE; + return false; } nvc0->blit->nvc0 = nvc0; nvc0->blit->rast.pipe.half_pixel_center = 1; - return TRUE; + return true; } void diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c index ddc0409ca86..d19082e0e15 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c @@ -34,8 +34,8 @@ (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK | \ NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK) -static INLINE uint32_t -nv50_tic_swizzle(uint32_t tc, unsigned swz, boolean tex_int) +static inline uint32_t +nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int) { switch (swz) { case PIPE_SWIZZLE_RED: @@ -82,7 +82,7 @@ nvc0_create_texture_view(struct pipe_context *pipe, uint32_t depth; struct nv50_tic_entry *view; struct nv50_miptree *mt; - boolean tex_int; + bool tex_int; view = MALLOC_STRUCT(nv50_tic_entry); if (!view) @@ -195,7 +195,7 @@ nvc0_create_texture_view(struct pipe_context *pipe, default: NOUVEAU_ERR("unexpected/invalid texture target: %d\n", mt->base.base.target); - return FALSE; + return false; } tic[3] = (flags & NV50_TEXVIEW_FILTER_MSAA8) ? 0x20000000 : 0x00300000; @@ -226,7 +226,7 @@ nvc0_create_texture_view(struct pipe_context *pipe, return &view->pipe; } -static boolean +static bool nvc0_validate_tic(struct nvc0_context *nvc0, int s) { uint32_t commands[32]; @@ -234,12 +234,12 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s) struct nouveau_bo *txc = nvc0->screen->txc; unsigned i; unsigned n = 0; - boolean need_flush = FALSE; + bool need_flush = false; for (i = 0; i < nvc0->num_textures[s]; ++i) { struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]); struct nv04_resource *res; - const boolean dirty = !!(nvc0->textures_dirty[s] & (1 << i)); + const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i)); if (!tic) { if (dirty) @@ -263,7 +263,7 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s) BEGIN_NIC0(push, NVC0_M2MF(DATA), 8); PUSH_DATAp(push, &tic->tic[0], 8); - need_flush = TRUE; + need_flush = true; } else if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1); @@ -295,18 +295,18 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s) return need_flush; } -static boolean +static bool nve4_validate_tic(struct nvc0_context *nvc0, unsigned s) { struct nouveau_bo *txc = nvc0->screen->txc; struct nouveau_pushbuf *push = nvc0->base.pushbuf; unsigned i; - boolean need_flush = FALSE; + bool need_flush = false; for (i = 0; i < nvc0->num_textures[s]; ++i) { struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]); struct nv04_resource *res; - const boolean dirty = !!(nvc0->textures_dirty[s] & (1 << i)); + const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i)); if (!tic) { nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID; @@ -328,7 +328,7 @@ nve4_validate_tic(struct nvc0_context *nvc0, unsigned s) PUSH_DATA (push, 0x1001); PUSH_DATAp(push, &tic->tic[0], 8); - need_flush = TRUE; + need_flush = true; } else if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1); @@ -356,16 +356,14 @@ nve4_validate_tic(struct nvc0_context *nvc0, unsigned s) void nvc0_validate_textures(struct nvc0_context *nvc0) { - boolean need_flush; - - if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) { - need_flush = nve4_validate_tic(nvc0, 0); - need_flush |= nve4_validate_tic(nvc0, 3); - need_flush |= nve4_validate_tic(nvc0, 4); - } else { - need_flush = nvc0_validate_tic(nvc0, 0); - need_flush |= nvc0_validate_tic(nvc0, 3); - need_flush |= nvc0_validate_tic(nvc0, 4); + bool need_flush = false; + int i; + + for (i = 0; i < 5; i++) { + if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) + need_flush |= nve4_validate_tic(nvc0, i); + else + need_flush |= nvc0_validate_tic(nvc0, i); } if (need_flush) { @@ -374,14 +372,14 @@ void nvc0_validate_textures(struct nvc0_context *nvc0) } } -static boolean +static bool nvc0_validate_tsc(struct nvc0_context *nvc0, int s) { uint32_t commands[16]; struct nouveau_pushbuf *push = nvc0->base.pushbuf; unsigned i; unsigned n = 0; - boolean need_flush = FALSE; + bool need_flush = false; for (i = 0; i < nvc0->num_samplers[s]; ++i) { struct nv50_tsc_entry *tsc = nv50_tsc_entry(nvc0->samplers[s][i]); @@ -398,7 +396,7 @@ nvc0_validate_tsc(struct nvc0_context *nvc0, int s) nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc, 65536 + tsc->id * 32, NV_VRAM_DOMAIN(&nvc0->screen->base), 32, tsc->tsc); - need_flush = TRUE; + need_flush = true; } nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32); @@ -418,13 +416,13 @@ nvc0_validate_tsc(struct nvc0_context *nvc0, int s) return need_flush; } -boolean +bool nve4_validate_tsc(struct nvc0_context *nvc0, int s) { struct nouveau_bo *txc = nvc0->screen->txc; struct nouveau_pushbuf *push = nvc0->base.pushbuf; unsigned i; - boolean need_flush = FALSE; + bool need_flush = false; for (i = 0; i < nvc0->num_samplers[s]; ++i) { struct nv50_tsc_entry *tsc = nv50_tsc_entry(nvc0->samplers[s][i]); @@ -447,7 +445,7 @@ nve4_validate_tsc(struct nvc0_context *nvc0, int s) PUSH_DATA (push, 0x1001); PUSH_DATAp(push, &tsc->tsc[0], 8); - need_flush = TRUE; + need_flush = true; } nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32); @@ -466,16 +464,14 @@ nve4_validate_tsc(struct nvc0_context *nvc0, int s) void nvc0_validate_samplers(struct nvc0_context *nvc0) { - boolean need_flush; - - if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) { - need_flush = nve4_validate_tsc(nvc0, 0); - need_flush |= nve4_validate_tsc(nvc0, 3); - need_flush |= nve4_validate_tsc(nvc0, 4); - } else { - need_flush = nvc0_validate_tsc(nvc0, 0); - need_flush |= nvc0_validate_tsc(nvc0, 3); - need_flush |= nvc0_validate_tsc(nvc0, 4); + bool need_flush = false; + int i; + + for (i = 0; i < 5; i++) { + if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) + need_flush |= nve4_validate_tsc(nvc0, i); + else + need_flush |= nvc0_validate_tsc(nvc0, i); } if (need_flush) { @@ -645,13 +641,13 @@ nve4_set_surface_info(struct nouveau_pushbuf *push, } } -static INLINE void +static inline void nvc0_update_surface_bindings(struct nvc0_context *nvc0) { /* TODO */ } -static INLINE void +static inline void nve4_update_surface_bindings(struct nvc0_context *nvc0) { /* TODO */ diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c index 45c6f7cc3ca..7cc5b4b1f48 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c @@ -329,17 +329,17 @@ nve4_m2mf_copy_linear(struct nouveau_context *nv, } -static INLINE boolean +static inline bool nvc0_mt_transfer_can_map_directly(struct nv50_miptree *mt) { if (mt->base.domain == NOUVEAU_BO_VRAM) - return FALSE; + return false; if (mt->base.base.usage != PIPE_USAGE_STAGING) - return FALSE; + return false; return !nouveau_bo_memtype(mt->base.bo); } -static INLINE boolean +static inline bool nvc0_mt_sync(struct nvc0_context *nvc0, struct nv50_miptree *mt, unsigned usage) { if (!mt->base.mm) { diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c index 8cf2584b0ce..6f9e7906713 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c @@ -61,8 +61,8 @@ nvc0_vertex_state_create(struct pipe_context *pipe, so->num_elements = num_elements; so->instance_elts = 0; so->instance_bufs = 0; - so->shared_slots = FALSE; - so->need_conversion = FALSE; + so->shared_slots = false; + so->need_conversion = false; memset(so->vb_access_size, 0, sizeof(so->vb_access_size)); @@ -93,7 +93,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe, return NULL; } so->element[i].state = nvc0_format_table[fmt].vtx; - so->need_conversion = TRUE; + so->need_conversion = true; } size = util_format_get_blocksize(fmt); @@ -141,7 +141,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe, if (so->instance_elts || src_offset_max >= (1 << 14)) return so; - so->shared_slots = TRUE; + so->shared_slots = true; for (i = 0; i < num_elements; ++i) { const unsigned b = elements[i].vertex_buffer_index; @@ -196,7 +196,7 @@ nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a) push->cur += 5; } -static INLINE void +static inline void nvc0_user_vbuf_range(struct nvc0_context *nvc0, int vbi, uint32_t *base, uint32_t *size) { @@ -214,7 +214,7 @@ nvc0_user_vbuf_range(struct nvc0_context *nvc0, int vbi, } } -static INLINE void +static inline void nvc0_release_user_vbufs(struct nvc0_context *nvc0) { if (nvc0->vbo_user) { @@ -265,7 +265,7 @@ nvc0_update_user_vbufs(struct nvc0_context *nvc0) PUSH_DATAh(push, address[b] + ve->src_offset); PUSH_DATA (push, address[b] + ve->src_offset); } - nvc0->base.vbo_dirty = TRUE; + nvc0->base.vbo_dirty = true; } static void @@ -419,7 +419,7 @@ nvc0_vertex_arrays_validate(struct nvc0_context *nvc0) uint32_t const_vbos; unsigned i; uint8_t vbo_mode; - boolean update_vertex; + bool update_vertex; nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX); @@ -529,7 +529,7 @@ nvc0_idxbuf_validate(struct nvc0_context *nvc0) #define NVC0_PRIM_GL_CASE(n) \ case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n -static INLINE unsigned +static inline unsigned nvc0_prim_gl(unsigned prim) { switch (prim) { @@ -547,8 +547,7 @@ nvc0_prim_gl(unsigned prim) NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY); NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY); NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY); - /* - NVC0_PRIM_GL_CASE(PATCHES); */ + NVC0_PRIM_GL_CASE(PATCHES); default: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS; } @@ -559,7 +558,7 @@ nvc0_draw_vbo_kick_notify(struct nouveau_pushbuf *push) { struct nvc0_screen *screen = push->user_priv; - nouveau_fence_update(&screen->base, TRUE); + nouveau_fence_update(&screen->base, true); NOUVEAU_DRV_STAT(&screen->base, pushbuf_count, 1); } @@ -695,7 +694,7 @@ nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push, } static void -nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten, +nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten, unsigned mode, unsigned start, unsigned count, unsigned instance_count, int32_t index_bias) { @@ -835,8 +834,8 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info) buf->bo, offset, NVC0_IB_ENTRY_1_NO_PREFETCH | size); } -static INLINE void -nvc0_update_prim_restart(struct nvc0_context *nvc0, boolean en, uint32_t index) +static inline void +nvc0_update_prim_restart(struct nvc0_context *nvc0, bool en, uint32_t index) { struct nouveau_pushbuf *push = nvc0->base.pushbuf; @@ -889,6 +888,12 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) } } + if (info->mode == PIPE_PRIM_PATCHES && + nvc0->state.patch_vertices != info->vertices_per_patch) { + nvc0->state.patch_vertices = info->vertices_per_patch; + IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices); + } + /* 8 as minimum to avoid immediate double validation of new buffers */ nvc0_state_validate(nvc0, ~0, 8); @@ -910,13 +915,13 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) continue; if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) - nvc0->cb_dirty = TRUE; + nvc0->cb_dirty = true; } } if (nvc0->cb_dirty) { IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011); - nvc0->cb_dirty = FALSE; + nvc0->cb_dirty = false; } if (nvc0->state.vbo_mode) { @@ -940,19 +945,19 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) if (!nvc0->vtxbuf[i].buffer) continue; if (nvc0->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) - nvc0->base.vbo_dirty = TRUE; + nvc0->base.vbo_dirty = true; } if (!nvc0->base.vbo_dirty && nvc0->idxbuf.buffer && nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) - nvc0->base.vbo_dirty = TRUE; + nvc0->base.vbo_dirty = true; nvc0_update_prim_restart(nvc0, info->primitive_restart, info->restart_index); if (nvc0->base.vbo_dirty) { if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS) IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0); - nvc0->base.vbo_dirty = FALSE; + nvc0->base.vbo_dirty = false; } if (unlikely(info->indirect)) { @@ -962,10 +967,10 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) nvc0_draw_stream_output(nvc0, info); } else if (info->indexed) { - boolean shorten = info->max_index <= 65535; + bool shorten = info->max_index <= 65535; if (info->primitive_restart && info->restart_index > 65535) - shorten = FALSE; + shorten = false; nvc0_draw_elements(nvc0, shorten, info->mode, info->start, info->count, diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c index f180087161d..8b23a4887da 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c @@ -21,12 +21,12 @@ struct push_context { uint32_t restart_index; uint32_t instance_id; - boolean prim_restart; - boolean need_vertex_id; + bool prim_restart; + bool need_vertex_id; struct { - boolean enabled; - boolean value; + bool enabled; + bool value; unsigned stride; const uint8_t *data; } edgeflag; @@ -47,7 +47,7 @@ nvc0_push_context_init(struct nvc0_context *nvc0, struct push_context *ctx) ctx->need_vertex_id = nvc0->vertprog->vp.need_vertex_id && (nvc0->vertex->num_elements < 32); - ctx->edgeflag.value = TRUE; + ctx->edgeflag.value = true; ctx->edgeflag.enabled = nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS; /* silence warnings */ @@ -55,7 +55,7 @@ nvc0_push_context_init(struct nvc0_context *nvc0, struct push_context *ctx) ctx->edgeflag.stride = 0; } -static INLINE void +static inline void nvc0_vertex_configure_translate(struct nvc0_context *nvc0, int32_t index_bias) { struct translate *translate = nvc0->vertex->translate; @@ -78,7 +78,7 @@ nvc0_vertex_configure_translate(struct nvc0_context *nvc0, int32_t index_bias) } } -static INLINE void +static inline void nvc0_push_map_idxbuf(struct push_context *ctx, struct nvc0_context *nvc0) { if (nvc0->idxbuf.buffer) { @@ -90,7 +90,7 @@ nvc0_push_map_idxbuf(struct push_context *ctx, struct nvc0_context *nvc0) } } -static INLINE void +static inline void nvc0_push_map_edgeflag(struct push_context *ctx, struct nvc0_context *nvc0, int32_t index_bias) { @@ -112,7 +112,7 @@ nvc0_push_map_edgeflag(struct push_context *ctx, struct nvc0_context *nvc0, ctx->edgeflag.data += (intptr_t)index_bias * vb->stride; } -static INLINE unsigned +static inline unsigned prim_restart_search_i08(const uint8_t *elts, unsigned push, uint8_t index) { unsigned i; @@ -120,7 +120,7 @@ prim_restart_search_i08(const uint8_t *elts, unsigned push, uint8_t index) return i; } -static INLINE unsigned +static inline unsigned prim_restart_search_i16(const uint16_t *elts, unsigned push, uint16_t index) { unsigned i; @@ -128,7 +128,7 @@ prim_restart_search_i16(const uint16_t *elts, unsigned push, uint16_t index) return i; } -static INLINE unsigned +static inline unsigned prim_restart_search_i32(const uint32_t *elts, unsigned push, uint32_t index) { unsigned i; @@ -136,21 +136,21 @@ prim_restart_search_i32(const uint32_t *elts, unsigned push, uint32_t index) return i; } -static INLINE boolean +static inline bool ef_value(const struct push_context *ctx, uint32_t index) { float *pf = (float *)&ctx->edgeflag.data[index * ctx->edgeflag.stride]; - return *pf ? TRUE : FALSE; + return *pf ? true : false; } -static INLINE boolean +static inline bool ef_toggle(struct push_context *ctx) { ctx->edgeflag.value = !ctx->edgeflag.value; return ctx->edgeflag.value; } -static INLINE unsigned +static inline unsigned ef_toggle_search_i08(struct push_context *ctx, const uint8_t *elts, unsigned n) { unsigned i; @@ -158,7 +158,7 @@ ef_toggle_search_i08(struct push_context *ctx, const uint8_t *elts, unsigned n) return i; } -static INLINE unsigned +static inline unsigned ef_toggle_search_i16(struct push_context *ctx, const uint16_t *elts, unsigned n) { unsigned i; @@ -166,7 +166,7 @@ ef_toggle_search_i16(struct push_context *ctx, const uint16_t *elts, unsigned n) return i; } -static INLINE unsigned +static inline unsigned ef_toggle_search_i32(struct push_context *ctx, const uint32_t *elts, unsigned n) { unsigned i; @@ -174,7 +174,7 @@ ef_toggle_search_i32(struct push_context *ctx, const uint32_t *elts, unsigned n) return i; } -static INLINE unsigned +static inline unsigned ef_toggle_search_seq(struct push_context *ctx, unsigned start, unsigned n) { unsigned i; @@ -182,7 +182,7 @@ ef_toggle_search_seq(struct push_context *ctx, unsigned start, unsigned n) return i; } -static INLINE void * +static inline void * nvc0_push_setup_vertex_array(struct nvc0_context *nvc0, const unsigned count) { struct nouveau_pushbuf *push = nvc0->base.pushbuf; @@ -409,7 +409,7 @@ disp_vertices_seq(struct push_context *ctx, unsigned start, unsigned count) #define NVC0_PRIM_GL_CASE(n) \ case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n -static INLINE unsigned +static inline unsigned nvc0_prim_gl(unsigned prim) { switch (prim) { @@ -427,8 +427,7 @@ nvc0_prim_gl(unsigned prim) NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY); NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY); NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY); - /* - NVC0_PRIM_GL_CASE(PATCHES); */ + NVC0_PRIM_GL_CASE(PATCHES); default: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS; } @@ -483,7 +482,7 @@ nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info) struct pipe_context *pipe = &nvc0->base.pipe; struct nvc0_so_target *targ; targ = nvc0_so_target(info->count_from_stream_output); - pipe->get_query_result(pipe, targ->pq, TRUE, (void *)&vert_count); + pipe->get_query_result(pipe, targ->pq, true, (void *)&vert_count); vert_count /= targ->stride; } ctx.idxbuf = NULL; /* shut up warnings */ @@ -560,7 +559,7 @@ nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info) NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_fallback_count, 1); } -static INLINE void +static inline void copy_indices_u8(uint32_t *dst, const uint8_t *elts, uint32_t bias, unsigned n) { unsigned i; @@ -568,7 +567,7 @@ copy_indices_u8(uint32_t *dst, const uint8_t *elts, uint32_t bias, unsigned n) dst[i] = elts[i] + bias; } -static INLINE void +static inline void copy_indices_u16(uint32_t *dst, const uint16_t *elts, uint32_t bias, unsigned n) { unsigned i; @@ -576,7 +575,7 @@ copy_indices_u16(uint32_t *dst, const uint16_t *elts, uint32_t bias, unsigned n) dst[i] = elts[i] + bias; } -static INLINE void +static inline void copy_indices_u32(uint32_t *dst, const uint32_t *elts, uint32_t bias, unsigned n) { unsigned i; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h index 725e889683f..4ea8ca3cfa2 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h @@ -15,14 +15,14 @@ #endif -static INLINE void +static inline void nv50_add_bufctx_resident_bo(struct nouveau_bufctx *bufctx, int bin, unsigned flags, struct nouveau_bo *bo) { nouveau_bufctx_refn(bufctx, bin, bo, flags)->priv = NULL; } -static INLINE void +static inline void nvc0_add_resident(struct nouveau_bufctx *bufctx, int bin, struct nv04_resource *res, unsigned flags) { @@ -38,7 +38,7 @@ nvc0_add_resident(struct nouveau_bufctx *bufctx, int bin, #define BCTX_REFN(bctx, bin, res, acc) \ nvc0_add_resident(bctx, NVC0_BIND_##bin, res, NOUVEAU_BO_##acc) -static INLINE void +static inline void PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) { struct nouveau_pushbuf_refn ref = { bo, flags }; @@ -69,46 +69,46 @@ PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) #define NVC0_3D_SERIALIZE NV50_GRAPH_SERIALIZE -static INLINE uint32_t +static inline uint32_t NVC0_FIFO_PKHDR_SQ(int subc, int mthd, unsigned size) { return 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2); } -static INLINE uint32_t +static inline uint32_t NVC0_FIFO_PKHDR_NI(int subc, int mthd, unsigned size) { return 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2); } -static INLINE uint32_t +static inline uint32_t NVC0_FIFO_PKHDR_IL(int subc, int mthd, uint16_t data) { assert(data < 0x2000); return 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2); } -static INLINE uint32_t +static inline uint32_t NVC0_FIFO_PKHDR_1I(int subc, int mthd, unsigned size) { return 0xa0000000 | (size << 16) | (subc << 13) | (mthd >> 2); } -static INLINE uint8_t +static inline uint8_t nouveau_bo_memtype(const struct nouveau_bo *bo) { return bo->config.nvc0.memtype; } -static INLINE void +static inline void PUSH_DATAh(struct nouveau_pushbuf *push, uint64_t data) { *push->cur++ = (uint32_t)(data >> 32); } -static INLINE void +static inline void BEGIN_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) { #ifndef NVC0_PUSH_EXPLICIT_SPACE_CHECKING @@ -117,7 +117,7 @@ BEGIN_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(subc, mthd, size)); } -static INLINE void +static inline void BEGIN_NIC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) { #ifndef NVC0_PUSH_EXPLICIT_SPACE_CHECKING @@ -126,7 +126,7 @@ BEGIN_NIC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) PUSH_DATA (push, NVC0_FIFO_PKHDR_NI(subc, mthd, size)); } -static INLINE void +static inline void BEGIN_1IC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) { #ifndef NVC0_PUSH_EXPLICIT_SPACE_CHECKING @@ -135,7 +135,7 @@ BEGIN_1IC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size) PUSH_DATA (push, NVC0_FIFO_PKHDR_1I(subc, mthd, size)); } -static INLINE void +static inline void IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, uint16_t data) { #ifndef NVC0_PUSH_EXPLICIT_SPACE_CHECKING diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c index fce02a7cc57..d3e5676873e 100644 --- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c +++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c @@ -250,7 +250,7 @@ nve4_compute_validate_surfaces(struct nvc0_context *nvc0) static void nve4_compute_validate_samplers(struct nvc0_context *nvc0) { - boolean need_flush = nve4_validate_tsc(nvc0, 5); + bool need_flush = nve4_validate_tsc(nvc0, 5); if (need_flush) { BEGIN_NVC0(nvc0->base.pushbuf, NVE4_COMPUTE(TSC_FLUSH), 1); PUSH_DATA (nvc0->base.pushbuf, 0); @@ -299,11 +299,11 @@ nve4_compute_set_tex_handles(struct nvc0_context *nvc0) } -static boolean +static bool nve4_compute_state_validate(struct nvc0_context *nvc0) { if (!nvc0_compute_validate_program(nvc0)) - return FALSE; + return false; if (nvc0->dirty_cp & NVC0_NEW_CP_TEXTURES) nve4_compute_validate_textures(nvc0); if (nvc0->dirty_cp & NVC0_NEW_CP_SAMPLERS) @@ -316,15 +316,15 @@ nve4_compute_state_validate(struct nvc0_context *nvc0) nvc0_validate_global_residents(nvc0, nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL); - nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, FALSE); + nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, false); nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_cp); if (unlikely(nouveau_pushbuf_validate(nvc0->base.pushbuf))) - return FALSE; + return false; if (unlikely(nvc0->state.flushed)) - nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, TRUE); + nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true); - return TRUE; + return true; } @@ -364,7 +364,7 @@ nve4_compute_upload_input(struct nvc0_context *nvc0, const void *input, PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB); } -static INLINE uint8_t +static inline uint8_t nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size) { if (shared_size > (32 << 10)) @@ -413,7 +413,7 @@ nve4_compute_setup_launch_desc(struct nvc0_context *nvc0, nve4_cp_launch_desc_set_cb(desc, 0, screen->parm, 0, NVE4_CP_INPUT_SIZE); } -static INLINE struct nve4_cp_launch_desc * +static inline struct nve4_cp_launch_desc * nve4_compute_alloc_launch_desc(struct nouveau_context *nv, struct nouveau_bo **pbo, uint64_t *pgpuaddr) { @@ -505,7 +505,7 @@ nve4_compute_validate_textures(struct nvc0_context *nvc0) for (i = 0; i < nvc0->num_textures[s]; ++i) { struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]); struct nv04_resource *res; - const boolean dirty = !!(nvc0->textures_dirty[s] & (1 << i)); + const bool dirty = !!(nvc0->textures_dirty[s] & (1 << i)); if (!tic) { nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID; @@ -575,18 +575,18 @@ nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc) { const uint32_t *data = (const uint32_t *)desc; unsigned i; - boolean zero = FALSE; + bool zero = false; debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n"); for (i = 0; i < sizeof(*desc); i += 4) { if (data[i / 4]) { debug_printf("[%x]: 0x%08x\n", i, data[i / 4]); - zero = FALSE; + zero = false; } else if (!zero) { debug_printf("...\n"); - zero = TRUE; + zero = true; } } @@ -606,7 +606,7 @@ nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc) for (i = 0; i < 8; ++i) { uint64_t address; uint32_t size = desc->cb[i].size; - boolean valid = !!(desc->cb_mask & (1 << i)); + bool valid = !!(desc->cb_mask & (1 << i)); address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l; diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.h b/src/gallium/drivers/nouveau/nvc0/nve4_compute.h index 4d7af54d860..7364a68a579 100644 --- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.h +++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.h @@ -68,7 +68,7 @@ struct nve4_cp_launch_desc u32 unk48[16]; }; -static INLINE void +static inline void nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc) { memset(desc, 0, sizeof(*desc)); @@ -78,7 +78,7 @@ nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc) desc->unk47_20 = 0x300; } -static INLINE void +static inline void nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc, unsigned index, struct nouveau_bo *bo, @@ -96,7 +96,7 @@ nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc, desc->cb_mask |= 1 << index; } -static INLINE void +static inline void nve4_cp_launch_desc_set_ctx_cb(struct nve4_cp_launch_desc *desc, unsigned index, const struct nvc0_constbuf *cb) |