diff options
Diffstat (limited to 'src/gallium/drivers/i965')
23 files changed, 329 insertions, 176 deletions
diff --git a/src/gallium/drivers/i965/SConscript b/src/gallium/drivers/i965/SConscript index 85c4d7ed22e..119f914a16d 100644 --- a/src/gallium/drivers/i965/SConscript +++ b/src/gallium/drivers/i965/SConscript @@ -2,6 +2,10 @@ Import('*') env = env.Clone() +if msvc: + print 'warning: not building i965g' + Return(); + i965 = env.ConvenienceLibrary( target = 'i965', source = [ @@ -50,7 +54,7 @@ i965 = env.ConvenienceLibrary( 'brw_sf_state.c', 'brw_state_batch.c', 'brw_state_cache.c', -# 'brw_state_debug.c', + 'brw_state_debug.c', 'brw_state_upload.c', 'brw_swtnl.c', 'brw_urb.c', diff --git a/src/gallium/drivers/i965/brw_batchbuffer.c b/src/gallium/drivers/i965/brw_batchbuffer.c index 003b1fd5bf0..e80067f3b19 100644 --- a/src/gallium/drivers/i965/brw_batchbuffer.c +++ b/src/gallium/drivers/i965/brw_batchbuffer.c @@ -161,8 +161,8 @@ brw_batchbuffer_emit_reloc(struct brw_batchbuffer *batch, int ret; if (batch->ptr - batch->map > batch->buf->size) { - debug_printf("bad relocation ptr %p map %p offset %d size %d\n", - batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size); + debug_printf("bad relocation ptr %p map %p offset %li size %i\n", + batch->ptr, batch->map, (long) (batch->ptr - batch->map), batch->buf->size); return PIPE_ERROR_OUT_OF_MEMORY; } diff --git a/src/gallium/drivers/i965/brw_context.h b/src/gallium/drivers/i965/brw_context.h index 94c9c443f05..56d351f97d1 100644 --- a/src/gallium/drivers/i965/brw_context.h +++ b/src/gallium/drivers/i965/brw_context.h @@ -576,6 +576,7 @@ struct brw_context */ struct pipe_resource *index_buffer; unsigned index_size; + unsigned index_offset; /* Updates are signalled by PIPE_NEW_INDEX_RANGE: */ diff --git a/src/gallium/drivers/i965/brw_disasm.c b/src/gallium/drivers/i965/brw_disasm.c index 4c8579365d5..28c83515ba9 100644 --- a/src/gallium/drivers/i965/brw_disasm.c +++ b/src/gallium/drivers/i965/brw_disasm.c @@ -239,7 +239,7 @@ char *imm_encoding[8] = { [2] = "UW", [3] = "W", [5] = "VF", - [5] = "V", + [6] = "V", [7] = "F" }; diff --git a/src/gallium/drivers/i965/brw_draw.c b/src/gallium/drivers/i965/brw_draw.c index 4625c2048f9..3ab9024c31e 100644 --- a/src/gallium/drivers/i965/brw_draw.c +++ b/src/gallium/drivers/i965/brw_draw.c @@ -142,7 +142,7 @@ static int brw_emit_prim(struct brw_context *brw, */ static int try_draw_range_elements(struct brw_context *brw, - struct pipe_resource *index_buffer, + boolean indexed, unsigned hw_prim, unsigned start, unsigned count) { @@ -165,7 +165,7 @@ try_draw_range_elements(struct brw_context *brw, if (ret) return ret; - ret = brw_emit_prim(brw, start, count, index_buffer != NULL, hw_prim); + ret = brw_emit_prim(brw, start, count, indexed, hw_prim); if (ret) return ret; @@ -177,91 +177,54 @@ try_draw_range_elements(struct brw_context *brw, static void -brw_draw_range_elements(struct pipe_context *pipe, - struct pipe_resource *index_buffer, - unsigned index_size, int index_bias, - unsigned min_index, - unsigned max_index, - unsigned mode, unsigned start, unsigned count) +brw_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) { struct brw_context *brw = brw_context(pipe); int ret; uint32_t hw_prim; - hw_prim = brw_set_prim(brw, mode); + hw_prim = brw_set_prim(brw, info->mode); if (BRW_DEBUG & DEBUG_PRIMS) debug_printf("PRIM: %s start %d count %d index_buffer %p\n", - u_prim_name(mode), start, count, (void *)index_buffer); + u_prim_name(info->mode), info->start, info->count, + (void *) brw->curr.index_buffer); - assert(index_bias == 0); + assert(info->index_bias == 0); - /* Potentially trigger upload of new index buffer. - * - * XXX: do we need to go through state validation to achieve this? - * Could just call upload code directly. + /* Potentially trigger upload of new index buffer range. + * XXX: do we really care? */ - if (brw->curr.index_buffer != index_buffer || - brw->curr.index_size != index_size) { - pipe_resource_reference( &brw->curr.index_buffer, index_buffer ); - brw->curr.index_size = index_size; - brw->state.dirty.mesa |= PIPE_NEW_INDEX_BUFFER; - } - - /* XXX: do we really care? - */ - if (brw->curr.min_index != min_index || - brw->curr.max_index != max_index) + if (brw->curr.min_index != info->min_index || + brw->curr.max_index != info->max_index) { - brw->curr.min_index = min_index; - brw->curr.max_index = max_index; + brw->curr.min_index = info->min_index; + brw->curr.max_index = info->max_index; brw->state.dirty.mesa |= PIPE_NEW_INDEX_RANGE; } /* Make a first attempt at drawing: */ - ret = try_draw_range_elements(brw, index_buffer, hw_prim, start, count ); + ret = try_draw_range_elements(brw, info->indexed, + hw_prim, info->start, info->count); /* Otherwise, flush and retry: */ if (ret != 0) { brw_context_flush( brw ); - ret = try_draw_range_elements(brw, index_buffer, hw_prim, start, count ); + ret = try_draw_range_elements(brw, info->indexed, + hw_prim, info->start, info->count); assert(ret == 0); } } -static void -brw_draw_elements(struct pipe_context *pipe, - struct pipe_resource *index_buffer, - unsigned index_size, int index_bias, - unsigned mode, - unsigned start, unsigned count) -{ - brw_draw_range_elements( pipe, index_buffer, - index_size, index_bias, - 0, 0xffffffff, - mode, - start, count ); -} - -static void -brw_draw_arrays(struct pipe_context *pipe, unsigned mode, - unsigned start, unsigned count) -{ - brw_draw_elements(pipe, NULL, 0, 0, mode, start, count); -} - - boolean brw_draw_init( struct brw_context *brw ) { /* Register our drawing function: */ - brw->base.draw_arrays = brw_draw_arrays; - brw->base.draw_elements = brw_draw_elements; - brw->base.draw_range_elements = brw_draw_range_elements; + brw->base.draw_vbo = brw_draw_vbo; /* Create helpers for uploading data in user buffers: */ diff --git a/src/gallium/drivers/i965/brw_draw_upload.c b/src/gallium/drivers/i965/brw_draw_upload.c index 337eee8cd9c..ebeb1e146aa 100644 --- a/src/gallium/drivers/i965/brw_draw_upload.c +++ b/src/gallium/drivers/i965/brw_draw_upload.c @@ -231,7 +231,7 @@ static int brw_prepare_indices(struct brw_context *brw) struct pipe_resource *upload_buf = NULL; struct brw_winsys_buffer *bo = NULL; GLuint offset; - GLuint index_size; + GLuint index_size, index_offset; GLuint ib_size; int ret; @@ -246,13 +246,14 @@ static int brw_prepare_indices(struct brw_context *brw) ib_size = index_buffer->width0; index_size = brw->curr.index_size; + index_offset = brw->curr.index_offset; /* Turn userbuffer into a proper hardware buffer? */ if (brw_buffer_is_user_buffer(index_buffer)) { ret = u_upload_buffer( brw->vb.upload_index, - 0, + index_offset, ib_size, index_buffer, &offset, @@ -269,7 +270,7 @@ static int brw_prepare_indices(struct brw_context *brw) else { bo = brw_buffer(index_buffer)->bo; ib_size = bo->size; - offset = 0; + offset = index_offset; } /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading the diff --git a/src/gallium/drivers/i965/brw_pipe_clear.c b/src/gallium/drivers/i965/brw_pipe_clear.c index abf507991e2..d5cff338a66 100644 --- a/src/gallium/drivers/i965/brw_pipe_clear.c +++ b/src/gallium/drivers/i965/brw_pipe_clear.c @@ -26,6 +26,7 @@ **************************************************************************/ #include "util/u_pack_color.h" +#include "util/u_math.h" #include "pipe/p_state.h" @@ -42,12 +43,12 @@ * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field * since that might include software renderbuffers or renderbuffers * which we're clearing with triangles. - * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear */ static enum pipe_error try_clear( struct brw_context *brw, struct brw_surface *surface, - unsigned value ) + unsigned value, + unsigned rgba_mask) { uint32_t BR13, CMD; int x1 = 0; @@ -67,12 +68,11 @@ try_clear( struct brw_context *brw, x1, y1, x2 - x1, y2 - y1); BR13 = 0xf0 << 16; - CMD = XY_COLOR_BLT_CMD | XY_BLT_WRITE_RGB | XY_BLT_WRITE_ALPHA; + CMD = XY_COLOR_BLT_CMD | rgba_mask; /* Setup the blit command */ if (cpp == 4) { BR13 |= BR13_8888; - CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; } else { assert(cpp == 2); @@ -121,24 +121,36 @@ static void color_clear(struct brw_context *brw, if (bsurface->cpp == 2) value.ui |= value.ui << 16; - ret = try_clear( brw, bsurface, value.ui ); + ret = try_clear( brw, bsurface, value.ui, + XY_BLT_WRITE_RGB | XY_BLT_WRITE_ALPHA ); if (ret != 0) { brw_context_flush( brw ); - ret = try_clear( brw, bsurface, value.ui ); + ret = try_clear( brw, bsurface, value.ui, + XY_BLT_WRITE_RGB | XY_BLT_WRITE_ALPHA ); assert( ret == 0 ); } } -static void zstencil_clear(struct brw_context *brw, +static void zstencil_clear(struct brw_context *brw, struct brw_surface *bsurface, + unsigned clear_flags, double depth, unsigned stencil ) { enum pipe_error ret; unsigned value; + unsigned mask = 0; + union fi tmp; + + if (clear_flags & PIPE_CLEAR_DEPTH) + mask |= XY_BLT_WRITE_RGB; switch (bsurface->base.format) { + case PIPE_FORMAT_Z32_FLOAT: + tmp.f = (float)depth; + value = tmp.ui; + break; case PIPE_FORMAT_Z24X8_UNORM: case PIPE_FORMAT_Z24_UNORM_S8_USCALED: value = ((unsigned)(depth * MASK24) & MASK24); @@ -152,24 +164,31 @@ static void zstencil_clear(struct brw_context *brw, } switch (bsurface->base.format) { + case PIPE_FORMAT_Z32_FLOAT: + mask |= XY_BLT_WRITE_ALPHA; + break; case PIPE_FORMAT_Z24X8_UNORM: + value = value | (stencil << 24); + mask |= XY_BLT_WRITE_ALPHA; + break; case PIPE_FORMAT_Z24_UNORM_S8_USCALED: value = value | (stencil << 24); + if (clear_flags & PIPE_CLEAR_STENCIL) + mask |= XY_BLT_WRITE_ALPHA; break; - case PIPE_FORMAT_Z16_UNORM: value = value | (value << 16); + mask |= XY_BLT_WRITE_ALPHA; break; - default: break; } - ret = try_clear( brw, bsurface, value ); + ret = try_clear( brw, bsurface, value, mask ); if (ret != 0) { brw_context_flush( brw ); - ret = try_clear( brw, bsurface, value ); + ret = try_clear( brw, bsurface, value, mask ); assert( ret == 0 ); } } @@ -201,15 +220,48 @@ static void brw_clear(struct pipe_context *pipe, if (brw->curr.fb.zsbuf) { zstencil_clear( brw, brw_surface(brw->curr.fb.zsbuf), + buffers & PIPE_CLEAR_DEPTHSTENCIL, depth, stencil ); } } } +/* XXX should respect region */ +static void brw_clear_render_target(struct pipe_context *pipe, + struct pipe_surface *dst, + const float *rgba, + unsigned dstx, unsigned dsty, + unsigned width, unsigned height) +{ + struct brw_context *brw = brw_context( pipe ); + + color_clear( brw, + brw_surface(dst), + rgba ); +} + +/* XXX should respect region */ +static void brw_clear_depth_stencil(struct pipe_context *pipe, + struct pipe_surface *dst, + unsigned clear_flags, + double depth, + unsigned stencil, + unsigned dstx, unsigned dsty, + unsigned width, unsigned height) +{ + struct brw_context *brw = brw_context( pipe ); + + zstencil_clear( brw, + brw_surface(dst), + clear_flags, + depth, stencil ); +} void brw_pipe_clear_init( struct brw_context *brw ) { brw->base.clear = brw_clear; + brw->base.clear_render_target = brw_clear_render_target; + brw->base.clear_depth_stencil = brw_clear_depth_stencil; } diff --git a/src/gallium/drivers/i965/brw_pipe_depth.c b/src/gallium/drivers/i965/brw_pipe_depth.c index b7000d5e334..31c2c343d89 100644 --- a/src/gallium/drivers/i965/brw_pipe_depth.c +++ b/src/gallium/drivers/i965/brw_pipe_depth.c @@ -167,12 +167,19 @@ static void brw_set_stencil_ref(struct pipe_context *pipe, brw->state.dirty.mesa |= PIPE_NEW_DEPTH_STENCIL_ALPHA; } +static void +brw_set_sample_mask(struct pipe_context *pipe, + unsigned sample_mask) +{ +} + void brw_pipe_depth_stencil_init( struct brw_context *brw ) { brw->base.set_stencil_ref = brw_set_stencil_ref; brw->base.create_depth_stencil_alpha_state = brw_create_depth_stencil_state; brw->base.bind_depth_stencil_alpha_state = brw_bind_depth_stencil_state; brw->base.delete_depth_stencil_alpha_state = brw_delete_depth_stencil_state; + brw->base.set_sample_mask = brw_set_sample_mask; } void brw_pipe_depth_stencil_cleanup( struct brw_context *brw ) diff --git a/src/gallium/drivers/i965/brw_pipe_query.c b/src/gallium/drivers/i965/brw_pipe_query.c index 2eb862635cc..0745254c3cc 100644 --- a/src/gallium/drivers/i965/brw_pipe_query.c +++ b/src/gallium/drivers/i965/brw_pipe_query.c @@ -50,10 +50,11 @@ static boolean brw_query_get_result(struct pipe_context *pipe, struct pipe_query *q, boolean wait, - uint64_t *result) + void *vresult) { struct brw_context *brw = brw_context(pipe); struct brw_query_object *query = (struct brw_query_object *)q; + uint64_t *result = (uint64_t*)vresult; /* Map and count the pixels from the current query BO */ if (query->bo) { diff --git a/src/gallium/drivers/i965/brw_pipe_rast.c b/src/gallium/drivers/i965/brw_pipe_rast.c index 2117e91a9e4..4c1a6d7dcdf 100644 --- a/src/gallium/drivers/i965/brw_pipe_rast.c +++ b/src/gallium/drivers/i965/brw_pipe_rast.c @@ -42,7 +42,7 @@ calculate_clip_key_rast( const struct brw_context *brw, key->do_flat_shading = templ->flatshade; - if (templ->cull_mode == PIPE_WINDING_BOTH) { + if (templ->cull_face == PIPE_FACE_FRONT_AND_BACK) { key->clip_mode = BRW_CLIPMODE_REJECT_ALL; return; } @@ -50,12 +50,18 @@ calculate_clip_key_rast( const struct brw_context *brw, key->fill_ccw = CLIP_CULL; key->fill_cw = CLIP_CULL; - if (!(templ->cull_mode & PIPE_WINDING_CCW)) { - key->fill_ccw = translate_fill(templ->fill_ccw); + if (!(templ->cull_face & PIPE_FACE_FRONT)) { + if (templ->front_ccw) + key->fill_ccw = translate_fill(templ->fill_front); + else + key->fill_cw = translate_fill(templ->fill_front); } - if (!(templ->cull_mode & PIPE_WINDING_CW)) { - key->fill_cw = translate_fill(templ->fill_cw); + if (!(templ->cull_face & PIPE_FACE_BACK)) { + if (templ->front_ccw) + key->fill_cw = translate_fill(templ->fill_back); + else + key->fill_ccw = translate_fill(templ->fill_back); } if (key->fill_cw == CLIP_LINE || @@ -66,8 +72,29 @@ calculate_clip_key_rast( const struct brw_context *brw, key->clip_mode = BRW_CLIPMODE_CLIP_NON_REJECTED; } - key->offset_ccw = templ->offset_ccw; - key->offset_cw = templ->offset_cw; + switch (key->fill_cw) { + case CLIP_POINT: + key->offset_cw = templ->offset_point; + break; + case CLIP_LINE: + key->offset_cw = templ->offset_line; + break; + case CLIP_FILL: + key->offset_cw = templ->offset_tri; + break; + } + + switch (key->fill_ccw) { + case CLIP_POINT: + key->offset_ccw = templ->offset_point; + break; + case CLIP_LINE: + key->offset_ccw = templ->offset_line; + break; + case CLIP_FILL: + key->offset_ccw = templ->offset_tri; + break; + } if (templ->light_twoside && key->fill_cw != CLIP_CULL) key->copy_bfc_cw = 1; @@ -111,12 +138,12 @@ static void *brw_create_rasterizer_state( struct pipe_context *pipe, /* Caclculate lookup value for WM IZ table. */ if (templ->line_smooth) { - if (templ->fill_cw == PIPE_POLYGON_MODE_LINE && - templ->fill_ccw == PIPE_POLYGON_MODE_LINE) { + if (templ->fill_front == PIPE_POLYGON_MODE_LINE && + templ->fill_back == PIPE_POLYGON_MODE_LINE) { rast->unfilled_aa_line = AA_ALWAYS; } - else if (templ->fill_cw == PIPE_POLYGON_MODE_LINE || - templ->fill_ccw == PIPE_POLYGON_MODE_LINE) { + else if (templ->fill_front == PIPE_POLYGON_MODE_LINE || + templ->fill_back == PIPE_POLYGON_MODE_LINE) { rast->unfilled_aa_line = AA_SOMETIMES; } else { diff --git a/src/gallium/drivers/i965/brw_pipe_vertex.c b/src/gallium/drivers/i965/brw_pipe_vertex.c index 4a120a51dad..007239efc40 100644 --- a/src/gallium/drivers/i965/brw_pipe_vertex.c +++ b/src/gallium/drivers/i965/brw_pipe_vertex.c @@ -274,10 +274,41 @@ static void brw_set_vertex_buffers(struct pipe_context *pipe, } +static void brw_set_index_buffer(struct pipe_context *pipe, + const struct pipe_index_buffer *ib) +{ + struct brw_context *brw = brw_context(pipe); + + if (ib) { + if (brw->curr.index_buffer == ib->buffer && + brw->curr.index_offset == ib->offset && + brw->curr.index_size == ib->index_size) + return; + + pipe_resource_reference(&brw->curr.index_buffer, ib->buffer); + brw->curr.index_offset = ib->offset; + brw->curr.index_size = ib->index_size; + } + else { + if (!brw->curr.index_buffer && + !brw->curr.index_offset && + !brw->curr.index_size) + return; + + pipe_resource_reference(&brw->curr.index_buffer, NULL); + brw->curr.index_offset = 0; + brw->curr.index_size = 0; + } + + brw->state.dirty.mesa |= PIPE_NEW_INDEX_BUFFER; +} + + void brw_pipe_vertex_init( struct brw_context *brw ) { brw->base.set_vertex_buffers = brw_set_vertex_buffers; + brw->base.set_index_buffer = brw_set_index_buffer; brw->base.create_vertex_elements_state = brw_create_vertex_elements_state; brw->base.bind_vertex_elements_state = brw_bind_vertex_elements_state; brw->base.delete_vertex_elements_state = brw_delete_vertex_elements_state; diff --git a/src/gallium/drivers/i965/brw_public.h b/src/gallium/drivers/i965/brw_public.h new file mode 100644 index 00000000000..be2cd6b5c4d --- /dev/null +++ b/src/gallium/drivers/i965/brw_public.h @@ -0,0 +1,13 @@ + +#ifndef BRW_PUBLIC_H +#define BRW_PUBLIC_H + +struct brw_winsys_screen; +struct pipe_screen; + +/** + * Create brw AKA i965 pipe_screen. + */ +struct pipe_screen * brw_screen_create(struct brw_winsys_screen *bws); + +#endif diff --git a/src/gallium/drivers/i965/brw_resource.c b/src/gallium/drivers/i965/brw_resource.c index d601f42dd16..3b61ffbd035 100644 --- a/src/gallium/drivers/i965/brw_resource.c +++ b/src/gallium/drivers/i965/brw_resource.c @@ -1,4 +1,5 @@ #include "util/u_debug.h" +#include "util/u_surface.h" #include "brw_resource.h" #include "brw_context.h" @@ -12,7 +13,7 @@ brw_resource_create(struct pipe_screen *screen, if (template->target == PIPE_BUFFER) return brw_buffer_create(screen, template); else - return brw_resource_create(screen, template); + return brw_texture_create(screen, template); } @@ -37,6 +38,7 @@ brw_init_resource_functions(struct brw_context *brw ) brw->base.transfer_unmap = u_transfer_unmap_vtbl; brw->base.transfer_destroy = u_transfer_destroy_vtbl; brw->base.transfer_inline_write = u_transfer_inline_write_vtbl; + brw->base.resource_copy_region = util_resource_copy_region; } void diff --git a/src/gallium/drivers/i965/brw_resource.h b/src/gallium/drivers/i965/brw_resource.h index 3390c270d42..78defb37b2a 100644 --- a/src/gallium/drivers/i965/brw_resource.h +++ b/src/gallium/drivers/i965/brw_resource.h @@ -124,7 +124,8 @@ boolean brw_is_format_supported( struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, - unsigned tex_usage, + unsigned sample_count, + unsigned tex_usage, unsigned geom_flags ); */ diff --git a/src/gallium/drivers/i965/brw_resource_texture.c b/src/gallium/drivers/i965/brw_resource_texture.c index 07537fe44ef..3860d18a7a2 100644 --- a/src/gallium/drivers/i965/brw_resource_texture.c +++ b/src/gallium/drivers/i965/brw_resource_texture.c @@ -66,6 +66,7 @@ static GLuint translate_tex_target( unsigned target ) return BRW_SURFACE_1D; case PIPE_TEXTURE_2D: + case PIPE_TEXTURE_RECT: return BRW_SURFACE_2D; case PIPE_TEXTURE_3D: @@ -210,7 +211,7 @@ brw_texture_get_handle(struct pipe_screen *screen, stride = tex->pitch * tex->cpp; - return bscreen->sws->bo_get_handle(tex->bo, whandle, stride); + return bscreen->sws->bo_get_handle(tex->bo, whandle, stride) == PIPE_OK; } @@ -498,7 +499,8 @@ brw_texture_from_handle(struct pipe_screen *screen, unsigned pitch; GLuint format; - if (template->target != PIPE_TEXTURE_2D || + if ((template->target != PIPE_TEXTURE_2D + && template->target != PIPE_TEXTURE_RECT) || template->last_level != 0 || template->depth0 != 1) return NULL; @@ -594,7 +596,8 @@ fail: boolean brw_is_format_supported( struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, - unsigned tex_usage, + unsigned sample_count, + unsigned tex_usage, unsigned geom_flags ) { return translate_tex_format(format) != BRW_SURFACEFORMAT_INVALID; diff --git a/src/gallium/drivers/i965/brw_screen.c b/src/gallium/drivers/i965/brw_screen.c index 0a7151bde44..864b21fa53c 100644 --- a/src/gallium/drivers/i965/brw_screen.c +++ b/src/gallium/drivers/i965/brw_screen.c @@ -34,43 +34,44 @@ #include "brw_context.h" #include "brw_screen.h" #include "brw_winsys.h" +#include "brw_public.h" #include "brw_debug.h" #include "brw_resource.h" #ifdef DEBUG static const struct debug_named_value debug_names[] = { - { "tex", DEBUG_TEXTURE}, - { "state", DEBUG_STATE}, - { "ioctl", DEBUG_IOCTL}, - { "blit", DEBUG_BLIT}, - { "curbe", DEBUG_CURBE}, - { "fall", DEBUG_FALLBACKS}, - { "verb", DEBUG_VERBOSE}, - { "bat", DEBUG_BATCH}, - { "pix", DEBUG_PIXEL}, - { "wins", DEBUG_WINSYS}, - { "min", DEBUG_MIN_URB}, - { "dis", DEBUG_DISASSEM}, - { "sync", DEBUG_SYNC}, - { "prim", DEBUG_PRIMS }, - { "vert", DEBUG_VERTS }, - { "dma", DEBUG_DMA }, - { "san", DEBUG_SANITY }, - { "sleep", DEBUG_SLEEP }, - { "stats", DEBUG_STATS }, - { "sing", DEBUG_SINGLE_THREAD }, - { "thre", DEBUG_SINGLE_THREAD }, - { "wm", DEBUG_WM }, - { "urb", DEBUG_URB }, - { "vs", DEBUG_VS }, - { NULL, 0 } + { "tex", DEBUG_TEXTURE, NULL }, + { "state", DEBUG_STATE, NULL }, + { "ioctl", DEBUG_IOCTL, NULL }, + { "blit", DEBUG_BLIT, NULL }, + { "curbe", DEBUG_CURBE, NULL }, + { "fall", DEBUG_FALLBACKS, NULL }, + { "verb", DEBUG_VERBOSE, NULL }, + { "bat", DEBUG_BATCH, NULL }, + { "pix", DEBUG_PIXEL, NULL }, + { "wins", DEBUG_WINSYS, NULL }, + { "min", DEBUG_MIN_URB, NULL }, + { "dis", DEBUG_DISASSEM, NULL }, + { "sync", DEBUG_SYNC, NULL }, + { "prim", DEBUG_PRIMS, NULL }, + { "vert", DEBUG_VERTS, NULL }, + { "dma", DEBUG_DMA, NULL }, + { "san", DEBUG_SANITY, NULL }, + { "sleep", DEBUG_SLEEP, NULL }, + { "stats", DEBUG_STATS, NULL }, + { "sing", DEBUG_SINGLE_THREAD, NULL }, + { "thre", DEBUG_SINGLE_THREAD, NULL }, + { "wm", DEBUG_WM, NULL }, + { "urb", DEBUG_URB, NULL }, + { "vs", DEBUG_VS, NULL }, + DEBUG_NAMED_VALUE_END }; static const struct debug_named_value dump_names[] = { - { "asm", DUMP_ASM}, - { "state", DUMP_STATE}, - { "batch", DUMP_BATCH}, - { NULL, 0 } + { "asm", DUMP_ASM, NULL }, + { "state", DUMP_STATE, NULL }, + { "batch", DUMP_BATCH, NULL }, + DEBUG_NAMED_VALUE_END }; int BRW_DEBUG = 0; @@ -149,7 +150,7 @@ brw_get_name(struct pipe_screen *screen) } static int -brw_get_param(struct pipe_screen *screen, int param) +brw_get_param(struct pipe_screen *screen, enum pipe_cap param) { switch (param) { case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: @@ -172,6 +173,8 @@ brw_get_param(struct pipe_screen *screen, int param) return 1; case PIPE_CAP_OCCLUSION_QUERY: return 0; + case PIPE_CAP_TIMER_QUERY: + return 0; case PIPE_CAP_TEXTURE_SHADOW_MAP: return 1; case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: @@ -186,13 +189,60 @@ brw_get_param(struct pipe_screen *screen, int param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: return 0; + case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: + /* disable for now */ + return 0; + default: + return 0; + } +} + +static int +brw_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param) +{ + switch(shader) { + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_FRAGMENT: + case PIPE_SHADER_GEOMETRY: + break; default: return 0; } + + /* XXX: these are just shader model 4.0 values, fix this! */ + switch(param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + return 65536; + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + return 65536; + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + return 65536; + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return 65536; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + return 65536; + case PIPE_SHADER_CAP_MAX_INPUTS: + return 32; + case PIPE_SHADER_CAP_MAX_CONSTS: + return 4096; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return PIPE_MAX_CONSTANT_BUFFERS; + case PIPE_SHADER_CAP_MAX_TEMPS: + return 4096; + case PIPE_SHADER_CAP_MAX_ADDRS: + return 0; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; + default: + assert(0); + return 0; + } } static float -brw_get_paramf(struct pipe_screen *screen, int param) +brw_get_paramf(struct pipe_screen *screen, enum pipe_cap param) { switch (param) { case PIPE_CAP_MAX_LINE_WIDTH: @@ -218,9 +268,10 @@ brw_get_paramf(struct pipe_screen *screen, int param) static boolean brw_is_format_supported(struct pipe_screen *screen, - enum pipe_format format, + enum pipe_format format, enum pipe_texture_target target, - unsigned tex_usage, + unsigned sample_count, + unsigned tex_usage, unsigned geom_flags) { static const enum pipe_format tex_supported[] = { @@ -276,6 +327,9 @@ brw_is_format_supported(struct pipe_screen *screen, const enum pipe_format *list; uint i; + if (sample_count > 1) + return FALSE; + if (tex_usage & PIPE_BIND_DEPTH_STENCIL) list = depth_supported; else if (tex_usage & PIPE_BIND_RENDER_TARGET) @@ -341,7 +395,7 @@ brw_destroy_screen(struct pipe_screen *screen) * Create a new brw_screen object */ struct pipe_screen * -brw_create_screen(struct brw_winsys_screen *sws, uint pci_id) +brw_screen_create(struct brw_winsys_screen *sws) { struct brw_screen *bscreen; struct brw_chipset chipset; @@ -356,9 +410,9 @@ brw_create_screen(struct brw_winsys_screen *sws, uint pci_id) memset(&chipset, 0, sizeof chipset); - chipset.pci_id = pci_id; + chipset.pci_id = sws->pci_id; - switch (pci_id) { + switch (chipset.pci_id) { case PCI_CHIP_I965_G: case PCI_CHIP_I965_Q: case PCI_CHIP_I965_G_1: @@ -384,7 +438,7 @@ brw_create_screen(struct brw_winsys_screen *sws, uint pci_id) default: debug_printf("%s: unknown pci id 0x%x, cannot create screen\n", - __FUNCTION__, pci_id); + __FUNCTION__, chipset.pci_id); return NULL; } @@ -400,6 +454,7 @@ brw_create_screen(struct brw_winsys_screen *sws, uint pci_id) bscreen->base.get_name = brw_get_name; bscreen->base.get_vendor = brw_get_vendor; bscreen->base.get_param = brw_get_param; + bscreen->base.get_shader_param = brw_get_shader_param; bscreen->base.get_paramf = brw_get_paramf; bscreen->base.is_format_supported = brw_is_format_supported; bscreen->base.context_create = brw_create_context; diff --git a/src/gallium/drivers/i965/brw_sf.c b/src/gallium/drivers/i965/brw_sf.c index 9cceb4dbe52..5abf3848ab4 100644 --- a/src/gallium/drivers/i965/brw_sf.c +++ b/src/gallium/drivers/i965/brw_sf.c @@ -166,8 +166,8 @@ static enum pipe_error upload_sf_prog(struct brw_context *brw) case PIPE_PRIM_TRIANGLES: /* PIPE_NEW_RAST */ - if (rast->fill_cw != PIPE_POLYGON_MODE_FILL || - rast->fill_ccw != PIPE_POLYGON_MODE_FILL) + if (rast->fill_front != PIPE_POLYGON_MODE_FILL || + rast->fill_back != PIPE_POLYGON_MODE_FILL) key.primitive = SF_UNFILLED_TRIS; else key.primitive = SF_TRIANGLES; @@ -187,7 +187,7 @@ static enum pipe_error upload_sf_prog(struct brw_context *brw) key.do_twoside_color = rast->light_twoside; if (key.do_twoside_color) { - key.frontface_ccw = (rast->front_winding == PIPE_WINDING_CCW); + key.frontface_ccw = rast->front_ccw; } if (brw_search_cache(&brw->cache, BRW_SF_PROG, diff --git a/src/gallium/drivers/i965/brw_sf_state.c b/src/gallium/drivers/i965/brw_sf_state.c index 0ad91e03072..6c299a86b49 100644 --- a/src/gallium/drivers/i965/brw_sf_state.c +++ b/src/gallium/drivers/i965/brw_sf_state.c @@ -89,8 +89,8 @@ struct brw_sf_unit_key { unsigned line_smooth:1; unsigned point_sprite:1; unsigned point_attenuated:1; - unsigned front_face:2; - unsigned cull_mode:2; + unsigned front_ccw:1; + unsigned cull_face:2; unsigned flatshade_first:1; unsigned gl_rasterization_rules:1; unsigned line_last_pixel_enable:1; @@ -115,8 +115,8 @@ sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key) /* PIPE_NEW_RAST */ key->scissor = rast->scissor; - key->front_face = rast->front_winding; - key->cull_mode = rast->cull_mode; + key->front_ccw = rast->front_ccw; + key->cull_face = rast->cull_face; key->line_smooth = rast->line_smooth; key->line_width = rast->line_width; key->flatshade_first = rast->flatshade_first; @@ -183,22 +183,22 @@ sf_unit_create_from_key(struct brw_context *brw, if (key->scissor) sf.sf6.scissor = 1; - if (key->front_face == PIPE_WINDING_CCW) + if (key->front_ccw) sf.sf5.front_winding = BRW_FRONTWINDING_CCW; else sf.sf5.front_winding = BRW_FRONTWINDING_CW; - switch (key->cull_mode) { - case PIPE_WINDING_CCW: - case PIPE_WINDING_CW: - sf.sf6.cull_mode = (key->front_face == key->cull_mode ? - BRW_CULLMODE_FRONT : - BRW_CULLMODE_BACK); + switch (key->cull_face) { + case PIPE_FACE_FRONT: + sf.sf6.cull_mode = BRW_CULLMODE_FRONT; break; - case PIPE_WINDING_BOTH: + case PIPE_FACE_BACK: + sf.sf6.cull_mode = BRW_CULLMODE_BACK; + break; + case PIPE_FACE_FRONT_AND_BACK: sf.sf6.cull_mode = BRW_CULLMODE_BOTH; break; - case PIPE_WINDING_NONE: + case PIPE_FACE_NONE: sf.sf6.cull_mode = BRW_CULLMODE_NONE; break; default: @@ -284,7 +284,7 @@ static enum pipe_error upload_sf_unit( struct brw_context *brw ) */ total_grf = (align(key.total_grf, 16) / 16 - 1); viewport_transform = 1; - front_winding = (key.front_face == PIPE_WINDING_CCW ? + front_winding = (key.front_ccw ? BRW_FRONTWINDING_CCW : BRW_FRONTWINDING_CW); diff --git a/src/gallium/drivers/i965/brw_winsys.h b/src/gallium/drivers/i965/brw_winsys.h index f30c7f18132..a06f8bb7d61 100644 --- a/src/gallium/drivers/i965/brw_winsys.h +++ b/src/gallium/drivers/i965/brw_winsys.h @@ -147,6 +147,7 @@ static INLINE void make_reloc(struct brw_winsys_reloc *reloc, struct brw_winsys_screen { + unsigned pci_id; /** * Buffer functions. @@ -261,12 +262,6 @@ bo_reference(struct brw_winsys_buffer **ptr, struct brw_winsys_buffer *buf) } -/** - * Create brw pipe_screen. - */ -struct pipe_screen *brw_create_screen(struct brw_winsys_screen *iws, unsigned pci_id); - - /************************************************************************* * Cooperative dumping between winsys and driver. TODO: make this diff --git a/src/gallium/drivers/i965/brw_wm_debug.c b/src/gallium/drivers/i965/brw_wm_debug.c index 3d11fa074cc..1b2aa93befc 100644 --- a/src/gallium/drivers/i965/brw_wm_debug.c +++ b/src/gallium/drivers/i965/brw_wm_debug.c @@ -101,16 +101,16 @@ void brw_wm_print_value( struct brw_wm_compile *c, debug_printf("undef"); else if( value - c->vreg >= 0 && value - c->vreg < BRW_WM_MAX_VREG) - debug_printf("r%d", value - c->vreg); + debug_printf("r%ld", (long) (value - c->vreg)); else if (value - c->creg >= 0 && value - c->creg < BRW_WM_MAX_PARAM) - debug_printf("c%d", value - c->creg); + debug_printf("c%ld", (long) (value - c->creg)); else if (value - c->payload.input_interp >= 0 && value - c->payload.input_interp < PIPE_MAX_SHADER_INPUTS) - debug_printf("i%d", value - c->payload.input_interp); + debug_printf("i%ld", (long) (value - c->payload.input_interp)); else if (value - c->payload.depth >= 0 && value - c->payload.depth < PIPE_MAX_SHADER_INPUTS) - debug_printf("d%d", value - c->payload.depth); + debug_printf("d%ld", (long) (value - c->payload.depth)); else debug_printf("?"); } @@ -202,7 +202,8 @@ static const char *file_strings[TGSI_FILE_COUNT+1] = { "SAMPLER", "ADDR", "IMM", - "LOOP", + "PRED", + "SV", "PAYLOAD" }; diff --git a/src/gallium/drivers/i965/brw_wm_fp.c b/src/gallium/drivers/i965/brw_wm_fp.c index 9c67759ad0b..f7ee55cc1c8 100644 --- a/src/gallium/drivers/i965/brw_wm_fp.c +++ b/src/gallium/drivers/i965/brw_wm_fp.c @@ -678,7 +678,7 @@ static void precalc_tex( struct brw_wm_compile *c, struct brw_fp_src src0, struct brw_fp_src sampler ) { - struct brw_fp_src coord = src_undef(); + struct brw_fp_src coord; struct brw_fp_dst tmp = dst_undef(); assert(unit < BRW_MAX_TEX_UNIT); diff --git a/src/gallium/drivers/i965/brw_wm_state.c b/src/gallium/drivers/i965/brw_wm_state.c index ee970ac75bc..efc2d96be13 100644 --- a/src/gallium/drivers/i965/brw_wm_state.c +++ b/src/gallium/drivers/i965/brw_wm_state.c @@ -128,8 +128,9 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) key->line_stipple = brw->curr.rast->templ.line_stipple_enable; - key->offset_enable = (brw->curr.rast->templ.offset_cw || - brw->curr.rast->templ.offset_ccw); + key->offset_enable = (brw->curr.rast->templ.offset_point || + brw->curr.rast->templ.offset_line || + brw->curr.rast->templ.offset_tri); key->offset_units = brw->curr.rast->templ.offset_units; key->offset_factor = brw->curr.rast->templ.offset_scale; diff --git a/src/gallium/drivers/i965/intel_decode.c b/src/gallium/drivers/i965/intel_decode.c index 6c47415cac5..36c04a31655 100644 --- a/src/gallium/drivers/i965/intel_decode.c +++ b/src/gallium/drivers/i965/intel_decode.c @@ -40,6 +40,8 @@ #include <stdint.h> #include <string.h> +#include "util/u_memory.h" +#include "util/u_string.h" #include "intel_decode.h" /*#include "intel_chipset.h"*/ @@ -115,8 +117,7 @@ decode_mi(const uint32_t *data, int count, uint32_t hw_offset, int *failures) }; - for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]); - opcode++) { + for (opcode = 0; opcode < Elements(opcodes_mi); opcode++) { if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) { unsigned int len = 1, i; @@ -274,8 +275,7 @@ decode_2d(const uint32_t *data, int count, uint32_t hw_offset, int *failures) return len; } - for (opcode = 0; opcode < sizeof(opcodes_2d) / sizeof(opcodes_2d[0]); - opcode++) { + for (opcode = 0; opcode < Elements(opcodes_2d); opcode++) { if ((data[0] & 0x1fc00000) >> 22 == opcodes_2d[opcode].opcode) { unsigned int i; @@ -478,7 +478,7 @@ i915_get_instruction_src0(const uint32_t *data, int i, char *srcname) char swizzle[100]; i915_get_instruction_src_name((a0 >> 7) & 0x7, src_nr, srcname); - sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); + util_snprintf(swizzle, sizeof(swizzle), ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); if (strcmp(swizzle, ".xyzw") != 0) strcat(srcname, swizzle); } @@ -496,7 +496,7 @@ i915_get_instruction_src1(const uint32_t *data, int i, char *srcname) char swizzle[100]; i915_get_instruction_src_name((a1 >> 13) & 0x7, src_nr, srcname); - sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); + util_snprintf(swizzle, sizeof(swizzle), ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); if (strcmp(swizzle, ".xyzw") != 0) strcat(srcname, swizzle); } @@ -513,7 +513,7 @@ i915_get_instruction_src2(const uint32_t *data, int i, char *srcname) char swizzle[100]; i915_get_instruction_src_name((a2 >> 21) & 0x7, src_nr, srcname); - sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); + util_snprintf(swizzle, sizeof(swizzle), ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); if (strcmp(swizzle, ".xyzw") != 0) strcat(srcname, swizzle); } @@ -642,7 +642,7 @@ i915_decode_dcl(const uint32_t *data, uint32_t hw_offset, int i, char *instr_pre switch ((d0 >> 19) & 0x3) { case 1: - sprintf(dcl_mask, ".%s%s%s%s", dcl_x, dcl_y, dcl_z, dcl_w); + util_snprintf(dcl_mask, sizeof(dcl_mask), ".%s%s%s%s", dcl_x, dcl_y, dcl_z, dcl_w); if (strcmp(dcl_mask, ".") == 0) fprintf(out, "bad (empty) dcl mask\n"); @@ -976,7 +976,7 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures, if (i + 3 >= count) BUFFER_FAIL(count, len, "3DSTATE_PIXEL_SHADER_PROGRAM"); - sprintf(instr_prefix, "PS%03d", instr); + util_snprintf(instr_prefix, sizeof(instr_prefix), "PS%03d", instr); i915_decode_instruction(data, hw_offset, i, instr_prefix); i += 3; } @@ -1036,9 +1036,7 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures, return len; } - for (opcode = 0; opcode < sizeof(opcodes_3d_1d) / sizeof(opcodes_3d_1d[0]); - opcode++) - { + for (opcode = 0; opcode < Elements(opcodes_3d_1d); opcode++) { if (opcodes_3d_1d[opcode].i830_only && !i830) continue; @@ -1290,8 +1288,7 @@ decode_3d(const uint32_t *data, int count, uint32_t hw_offset, int *failures) return decode_3d_1c(data, count, hw_offset, failures); } - for (opcode = 0; opcode < sizeof(opcodes_3d) / sizeof(opcodes_3d[0]); - opcode++) { + for (opcode = 0; opcode < Elements(opcodes_3d); opcode++) { if ((data[0] & 0x1f000000) >> 24 == opcodes_3d[opcode].opcode) { unsigned int len = 1, i; @@ -1636,8 +1633,7 @@ decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, int *failures return len; } - for (opcode = 0; opcode < sizeof(opcodes_3d) / sizeof(opcodes_3d[0]); - opcode++) { + for (opcode = 0; opcode < Elements(opcodes_3d); opcode++) { if ((data[0] & 0xffff0000) >> 16 == opcodes_3d[opcode].opcode) { unsigned int i; len = 1; @@ -1704,8 +1700,7 @@ decode_3d_i830(const uint32_t *data, int count, uint32_t hw_offset, int *failure return decode_3d_1c(data, count, hw_offset, failures); } - for (opcode = 0; opcode < sizeof(opcodes_3d) / sizeof(opcodes_3d[0]); - opcode++) { + for (opcode = 0; opcode < Elements(opcodes_3d); opcode++) { if ((data[0] & 0x1f000000) >> 24 == opcodes_3d[opcode].opcode) { unsigned int len = 1, i; |