diff options
Diffstat (limited to 'src/gallium/drivers/etnaviv/hw/state_3d.xml.h')
| -rw-r--r-- | src/gallium/drivers/etnaviv/hw/state_3d.xml.h | 402 |
1 files changed, 243 insertions, 159 deletions
diff --git a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h index 9084e643d3c..c5722aafa1b 100644 --- a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h +++ b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h @@ -8,13 +8,15 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 26245 bytes, from 2017-10-05 21:32:06) -- common.xml ( 26135 bytes, from 2017-10-05 21:20:32) -- state_hi.xml ( 27733 bytes, from 2017-10-05 21:20:32) -- copyright.xml ( 1597 bytes, from 2016-11-13 13:46:17) -- state_2d.xml ( 51552 bytes, from 2016-11-13 13:46:17) -- state_3d.xml ( 80819 bytes, from 2017-10-05 21:20:32) -- state_vg.xml ( 5975 bytes, from 2016-11-13 13:46:17) +- state.xml ( 26087 bytes, from 2017-10-30 13:44:54) +- common.xml ( 26187 bytes, from 2017-10-31 19:05:01) +- common_3d.xml ( 14547 bytes, from 2017-11-01 16:08:07) +- state_hi.xml ( 27733 bytes, from 2017-10-02 19:00:30) +- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22) +- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22) +- state_3d.xml ( 79520 bytes, from 2017-10-31 19:05:01) +- state_blt.xml ( 13405 bytes, from 2017-10-16 17:42:46) +- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22) Copyright (C) 2012-2017 by the following authors: - Wladimir J. van der Laan <[email protected]> @@ -87,6 +89,7 @@ DEALINGS IN THE SOFTWARE. #define RS_FORMAT_X8R8G8B8 0x00000005 #define RS_FORMAT_A8R8G8B8 0x00000006 #define RS_FORMAT_YUY2 0x00000007 +#define RS_FORMAT_A8 0x00000010 #define RS_FORMAT_R16F 0x00000011 #define RS_FORMAT_G16R16F 0x00000012 #define RS_FORMAT_A16B16G16R16F 0x00000013 @@ -103,85 +106,6 @@ DEALINGS IN THE SOFTWARE. #define RS_FORMAT_A2B10G10R10UI 0x0000001e #define RS_FORMAT_G8R8 0x0000001f #define RS_FORMAT_R8 0x00000023 -#define TEXTURE_FORMAT_NONE 0x00000000 -#define TEXTURE_FORMAT_A8 0x00000001 -#define TEXTURE_FORMAT_L8 0x00000002 -#define TEXTURE_FORMAT_I8 0x00000003 -#define TEXTURE_FORMAT_A8L8 0x00000004 -#define TEXTURE_FORMAT_A4R4G4B4 0x00000005 -#define TEXTURE_FORMAT_X4R4G4B4 0x00000006 -#define TEXTURE_FORMAT_A8R8G8B8 0x00000007 -#define TEXTURE_FORMAT_X8R8G8B8 0x00000008 -#define TEXTURE_FORMAT_A8B8G8R8 0x00000009 -#define TEXTURE_FORMAT_X8B8G8R8 0x0000000a -#define TEXTURE_FORMAT_R5G6B5 0x0000000b -#define TEXTURE_FORMAT_A1R5G5B5 0x0000000c -#define TEXTURE_FORMAT_X1R5G5B5 0x0000000d -#define TEXTURE_FORMAT_YUY2 0x0000000e -#define TEXTURE_FORMAT_UYVY 0x0000000f -#define TEXTURE_FORMAT_D16 0x00000010 -#define TEXTURE_FORMAT_D24S8 0x00000011 -#define TEXTURE_FORMAT_DXT1 0x00000013 -#define TEXTURE_FORMAT_DXT2_DXT3 0x00000014 -#define TEXTURE_FORMAT_DXT4_DXT5 0x00000015 -#define TEXTURE_FORMAT_E5B9G9R9 0x0000001d -#define TEXTURE_FORMAT_ETC1 0x0000001e -#define TEXTURE_FORMAT_EXT_NONE 0x00000000 -#define TEXTURE_FORMAT_EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 0x00000001 -#define TEXTURE_FORMAT_EXT_RGBA8_ETC2_EAC 0x00000002 -#define TEXTURE_FORMAT_EXT_R11_EAC 0x00000003 -#define TEXTURE_FORMAT_EXT_RG11_EAC 0x00000004 -#define TEXTURE_FORMAT_EXT_SIGNED_RG11_EAC 0x00000005 -#define TEXTURE_FORMAT_EXT_G8R8 0x00000006 -#define TEXTURE_FORMAT_EXT_R16F 0x00000007 -#define TEXTURE_FORMAT_EXT_G16R16F 0x00000008 -#define TEXTURE_FORMAT_EXT_A16B16G16R16F 0x00000009 -#define TEXTURE_FORMAT_EXT_R32F 0x0000000a -#define TEXTURE_FORMAT_EXT_G32R32F 0x0000000b -#define TEXTURE_FORMAT_EXT_A2B10G10R10 0x0000000c -#define TEXTURE_FORMAT_EXT_SIGNED_R11_EAC 0x0000000d -#define TEXTURE_FORMAT_EXT_R8_SNORM 0x0000000e -#define TEXTURE_FORMAT_EXT_G8R8_SNORM 0x0000000f -#define TEXTURE_FORMAT_EXT_X8B8G8R8_SNORM 0x00000010 -#define TEXTURE_FORMAT_EXT_A8B8G8R8_SNORM 0x00000011 -#define TEXTURE_FORMAT_EXT_ASTC 0x00000014 -#define TEXTURE_FORMAT_EXT_R8I 0x00000015 -#define TEXTURE_FORMAT_EXT_G8R8I 0x00000016 -#define TEXTURE_FORMAT_EXT_A8B8G8R8I 0x00000017 -#define TEXTURE_FORMAT_EXT_R16I 0x00000018 -#define TEXTURE_FORMAT_EXT_G16R16I 0x00000019 -#define TEXTURE_FORMAT_EXT_A16B16G16R16I 0x0000001a -#define TEXTURE_FORMAT_EXT_B10G11R11F 0x0000001b -#define TEXTURE_FORMAT_EXT_A2B10G10R10UI 0x0000001c -#define TEXTURE_FILTER_NONE 0x00000000 -#define TEXTURE_FILTER_NEAREST 0x00000001 -#define TEXTURE_FILTER_LINEAR 0x00000002 -#define TEXTURE_FILTER_ANISOTROPIC 0x00000003 -#define TEXTURE_TYPE_NONE 0x00000000 -#define TEXTURE_TYPE_1D 0x00000001 -#define TEXTURE_TYPE_2D 0x00000002 -#define TEXTURE_TYPE_3D 0x00000003 -#define TEXTURE_TYPE_CUBE_MAP 0x00000005 -#define TEXTURE_WRAPMODE_REPEAT 0x00000000 -#define TEXTURE_WRAPMODE_MIRRORED_REPEAT 0x00000001 -#define TEXTURE_WRAPMODE_CLAMP_TO_EDGE 0x00000002 -#define TEXTURE_FACE_POS_X 0x00000000 -#define TEXTURE_FACE_NEG_X 0x00000001 -#define TEXTURE_FACE_POS_Y 0x00000002 -#define TEXTURE_FACE_NEG_Y 0x00000003 -#define TEXTURE_FACE_POS_Z 0x00000004 -#define TEXTURE_FACE_NEG_Z 0x00000005 -#define TEXTURE_SWIZZLE_RED 0x00000000 -#define TEXTURE_SWIZZLE_GREEN 0x00000001 -#define TEXTURE_SWIZZLE_BLUE 0x00000002 -#define TEXTURE_SWIZZLE_ALPHA 0x00000003 -#define TEXTURE_SWIZZLE_ZERO 0x00000004 -#define TEXTURE_SWIZZLE_ONE 0x00000005 -#define TEXTURE_HALIGN_FOUR 0x00000000 -#define TEXTURE_HALIGN_SIXTEEN 0x00000001 -#define TEXTURE_HALIGN_SUPER_TILED 0x00000002 -#define TEXTURE_HALIGN_SPLIT_TILED 0x00000003 -#define TEXTURE_HALIGN_SPLIT_SUPER_TILED 0x00000004 #define LOGIC_OP_CLEAR 0x00000000 #define LOGIC_OP_NOR 0x00000001 #define LOGIC_OP_AND_INVERTED 0x00000002 @@ -198,6 +122,30 @@ DEALINGS IN THE SOFTWARE. #define LOGIC_OP_OR_REVERSE 0x0000000d #define LOGIC_OP_OR 0x0000000e #define LOGIC_OP_SET 0x0000000f +#define VARYING_NUM_COMPONENTS_VAR0__MASK 0x00000007 +#define VARYING_NUM_COMPONENTS_VAR0__SHIFT 0 +#define VARYING_NUM_COMPONENTS_VAR0(x) (((x) << VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VARYING_NUM_COMPONENTS_VAR0__MASK) +#define VARYING_NUM_COMPONENTS_VAR1__MASK 0x00000070 +#define VARYING_NUM_COMPONENTS_VAR1__SHIFT 4 +#define VARYING_NUM_COMPONENTS_VAR1(x) (((x) << VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VARYING_NUM_COMPONENTS_VAR1__MASK) +#define VARYING_NUM_COMPONENTS_VAR2__MASK 0x00000700 +#define VARYING_NUM_COMPONENTS_VAR2__SHIFT 8 +#define VARYING_NUM_COMPONENTS_VAR2(x) (((x) << VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VARYING_NUM_COMPONENTS_VAR2__MASK) +#define VARYING_NUM_COMPONENTS_VAR3__MASK 0x00007000 +#define VARYING_NUM_COMPONENTS_VAR3__SHIFT 12 +#define VARYING_NUM_COMPONENTS_VAR3(x) (((x) << VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VARYING_NUM_COMPONENTS_VAR3__MASK) +#define VARYING_NUM_COMPONENTS_VAR4__MASK 0x00070000 +#define VARYING_NUM_COMPONENTS_VAR4__SHIFT 16 +#define VARYING_NUM_COMPONENTS_VAR4(x) (((x) << VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VARYING_NUM_COMPONENTS_VAR4__MASK) +#define VARYING_NUM_COMPONENTS_VAR5__MASK 0x00700000 +#define VARYING_NUM_COMPONENTS_VAR5__SHIFT 20 +#define VARYING_NUM_COMPONENTS_VAR5(x) (((x) << VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VARYING_NUM_COMPONENTS_VAR5__MASK) +#define VARYING_NUM_COMPONENTS_VAR6__MASK 0x07000000 +#define VARYING_NUM_COMPONENTS_VAR6__SHIFT 24 +#define VARYING_NUM_COMPONENTS_VAR6(x) (((x) << VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VARYING_NUM_COMPONENTS_VAR6__MASK) +#define VARYING_NUM_COMPONENTS_VAR7__MASK 0x70000000 +#define VARYING_NUM_COMPONENTS_VAR7__SHIFT 28 +#define VARYING_NUM_COMPONENTS_VAR7(x) (((x) << VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VARYING_NUM_COMPONENTS_VAR7__MASK) #define VIVS_VS 0x00000000 #define VIVS_VS_END_PC 0x00000800 @@ -284,7 +232,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_UNIFORM_CACHE 0x00000860 #define VIVS_VS_UNIFORM_CACHE_FLUSH 0x00000001 #define VIVS_VS_UNIFORM_CACHE_PS 0x00000010 -#define VIVS_VS_UNIFORM_CACHE_UNK12 0x00001000 +#define VIVS_VS_UNIFORM_CACHE_RTNE_ROUNDING 0x00001000 #define VIVS_VS_UNIFORM_BASE 0x00000864 @@ -295,19 +243,23 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_INST_ADDR 0x0000086c -#define VIVS_VS_HALTI5_UNK00870 0x00000870 +#define VIVS_VS_HALTI5_OUTPUT_COUNT 0x00000870 +#define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK 0x000003ff +#define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT 0 +#define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT(x) (((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK) +#define VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK 0x0007ff00 +#define VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT 8 +#define VIVS_VS_HALTI5_OUTPUT_COUNT_B(x) (((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK) -#define VIVS_VS_HALTI5_UNK00874 0x00000874 +#define VIVS_VS_NEWRANGE_LOW 0x00000874 #define VIVS_VS_HALTI5_UNK00878 0x00000878 -#define VIVS_VS_HALTI5_UNK0087C 0x0000087c - #define VIVS_VS_HALTI5_UNK00880 0x00000880 #define VIVS_VS_HALTI1_UNK00884 0x00000884 -#define VIVS_VS_UNK0088C 0x0000088c +#define VIVS_VS_ICACHE_PREFETCH 0x0000088c #define VIVS_VS_ICACHE_UNK00890 0x00000890 @@ -316,8 +268,17 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_HALTI5_UNK00898__LEN 0x00000002 #define VIVS_VS_HALTI5_UNK008A0 0x000008a0 - -#define VIVS_VS_HALTI5_UNK008A8 0x000008a8 +#define VIVS_VS_HALTI5_UNK008A0_A__MASK 0x0000003f +#define VIVS_VS_HALTI5_UNK008A0_A__SHIFT 0 +#define VIVS_VS_HALTI5_UNK008A0_A(x) (((x) << VIVS_VS_HALTI5_UNK008A0_A__SHIFT) & VIVS_VS_HALTI5_UNK008A0_A__MASK) +#define VIVS_VS_HALTI5_UNK008A0_B__MASK 0x0007f000 +#define VIVS_VS_HALTI5_UNK008A0_B__SHIFT 12 +#define VIVS_VS_HALTI5_UNK008A0_B(x) (((x) << VIVS_VS_HALTI5_UNK008A0_B__SHIFT) & VIVS_VS_HALTI5_UNK008A0_B__MASK) +#define VIVS_VS_HALTI5_UNK008A0_C__MASK 0x1ff00000 +#define VIVS_VS_HALTI5_UNK008A0_C__SHIFT 20 +#define VIVS_VS_HALTI5_UNK008A0_C(x) (((x) << VIVS_VS_HALTI5_UNK008A0_C__SHIFT) & VIVS_VS_HALTI5_UNK008A0_C__MASK) + +#define VIVS_VS_SAMPLER_BASE 0x000008a8 #define VIVS_VS_ICACHE_INVALIDATE 0x000008b0 #define VIVS_VS_ICACHE_INVALIDATE_UNK0 0x00000001 @@ -328,15 +289,39 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_HALTI5_UNK008B8 0x000008b8 -#define VIVS_VS_HALTI5_UNK008BC 0x000008bc - -#define VIVS_VS_HALTI5_UNK008C0(i0) (0x000008c0 + 0x4*(i0)) -#define VIVS_VS_HALTI5_UNK008C0__ESIZE 0x00000004 -#define VIVS_VS_HALTI5_UNK008C0__LEN 0x00000008 - -#define VIVS_VS_HALTI5_UNK008E0(i0) (0x000008e0 + 0x4*(i0)) -#define VIVS_VS_HALTI5_UNK008E0__ESIZE 0x00000004 -#define VIVS_VS_HALTI5_UNK008E0__LEN 0x00000008 +#define VIVS_VS_NEWRANGE_HIGH 0x000008bc + +#define VIVS_VS_HALTI5_INPUT(i0) (0x000008c0 + 0x4*(i0)) +#define VIVS_VS_HALTI5_INPUT__ESIZE 0x00000004 +#define VIVS_VS_HALTI5_INPUT__LEN 0x00000008 +#define VIVS_VS_HALTI5_INPUT_I0__MASK 0x000000ff +#define VIVS_VS_HALTI5_INPUT_I0__SHIFT 0 +#define VIVS_VS_HALTI5_INPUT_I0(x) (((x) << VIVS_VS_HALTI5_INPUT_I0__SHIFT) & VIVS_VS_HALTI5_INPUT_I0__MASK) +#define VIVS_VS_HALTI5_INPUT_I1__MASK 0x0000ff00 +#define VIVS_VS_HALTI5_INPUT_I1__SHIFT 8 +#define VIVS_VS_HALTI5_INPUT_I1(x) (((x) << VIVS_VS_HALTI5_INPUT_I1__SHIFT) & VIVS_VS_HALTI5_INPUT_I1__MASK) +#define VIVS_VS_HALTI5_INPUT_I2__MASK 0x00ff0000 +#define VIVS_VS_HALTI5_INPUT_I2__SHIFT 16 +#define VIVS_VS_HALTI5_INPUT_I2(x) (((x) << VIVS_VS_HALTI5_INPUT_I2__SHIFT) & VIVS_VS_HALTI5_INPUT_I2__MASK) +#define VIVS_VS_HALTI5_INPUT_I3__MASK 0xff000000 +#define VIVS_VS_HALTI5_INPUT_I3__SHIFT 24 +#define VIVS_VS_HALTI5_INPUT_I3(x) (((x) << VIVS_VS_HALTI5_INPUT_I3__SHIFT) & VIVS_VS_HALTI5_INPUT_I3__MASK) + +#define VIVS_VS_HALTI5_OUTPUT(i0) (0x000008e0 + 0x4*(i0)) +#define VIVS_VS_HALTI5_OUTPUT__ESIZE 0x00000004 +#define VIVS_VS_HALTI5_OUTPUT__LEN 0x00000008 +#define VIVS_VS_HALTI5_OUTPUT_O0__MASK 0x000000ff +#define VIVS_VS_HALTI5_OUTPUT_O0__SHIFT 0 +#define VIVS_VS_HALTI5_OUTPUT_O0(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O0__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O0__MASK) +#define VIVS_VS_HALTI5_OUTPUT_O1__MASK 0x0000ff00 +#define VIVS_VS_HALTI5_OUTPUT_O1__SHIFT 8 +#define VIVS_VS_HALTI5_OUTPUT_O1(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O1__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O1__MASK) +#define VIVS_VS_HALTI5_OUTPUT_O2__MASK 0x00ff0000 +#define VIVS_VS_HALTI5_OUTPUT_O2__SHIFT 16 +#define VIVS_VS_HALTI5_OUTPUT_O2(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O2__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O2__MASK) +#define VIVS_VS_HALTI5_OUTPUT_O3__MASK 0xff000000 +#define VIVS_VS_HALTI5_OUTPUT_O3__SHIFT 24 +#define VIVS_VS_HALTI5_OUTPUT_O3(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O3__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O3__MASK) #define VIVS_VS_INST_MEM(i0) (0x00004000 + 0x4*(i0)) #define VIVS_VS_INST_MEM__ESIZE 0x00000004 @@ -346,9 +331,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_UNIFORMS__ESIZE 0x00000004 #define VIVS_VS_UNIFORMS__LEN 0x00000400 -#define VIVS_VS_HALTI5_UNK15600 0x00015600 - -#define VIVS_VS_HALTI5_UNK15604 0x00015604 +#define VIVS_VS_ICACHE_COUNT 0x00015604 #define VIVS_CL 0x00000000 @@ -531,11 +514,11 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PA_ZFARCLIPPING 0x00000a8c -#define VIVS_PA_HALTI5_UNK00A90(i0) (0x00000a90 + 0x4*(i0)) -#define VIVS_PA_HALTI5_UNK00A90__ESIZE 0x00000004 -#define VIVS_PA_HALTI5_UNK00A90__LEN 0x00000004 +#define VIVS_PA_VARYING_NUM_COMPONENTS(i0) (0x00000a90 + 0x4*(i0)) +#define VIVS_PA_VARYING_NUM_COMPONENTS__ESIZE 0x00000004 +#define VIVS_PA_VARYING_NUM_COMPONENTS__LEN 0x00000004 -#define VIVS_PA_HALTI5_UNK00AA8 0x00000aa8 +#define VIVS_PA_VS_OUTPUT_COUNT 0x00000aa8 #define VIVS_SE 0x00000000 @@ -603,6 +586,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_INPUT_COUNT_UNK8__MASK 0x00001f00 #define VIVS_PS_INPUT_COUNT_UNK8__SHIFT 8 #define VIVS_PS_INPUT_COUNT_UNK8(x) (((x) << VIVS_PS_INPUT_COUNT_UNK8__SHIFT) & VIVS_PS_INPUT_COUNT_UNK8__MASK) +#define VIVS_PS_INPUT_COUNT_DUAL16 0x00010000 #define VIVS_PS_TEMP_REGISTER_CONTROL 0x0000100c #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f @@ -646,21 +630,23 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_UNK01040__ESIZE 0x00000004 #define VIVS_PS_UNK01040__LEN 0x00000002 -#define VIVS_PS_UNK01048 0x00001048 +#define VIVS_PS_ICACHE_PREFETCH 0x00001048 #define VIVS_PS_ICACHE_UNK0104C 0x0000104c -#define VIVS_PS_HALTI4_UNK01054 0x00001054 +#define VIVS_PS_MSAA_CONFIG 0x00001054 + +#define VIVS_PS_SAMPLER_BASE 0x00001058 -#define VIVS_PS_HALTI5_UNK01058 0x00001058 +#define VIVS_PS_VARYING_NUM_COMPONENTS(i0) (0x00001080 + 0x4*(i0)) +#define VIVS_PS_VARYING_NUM_COMPONENTS__ESIZE 0x00000004 +#define VIVS_PS_VARYING_NUM_COMPONENTS__LEN 0x00000004 -#define VIVS_PS_HALTI5_UNK01080(i0) (0x00001080 + 0x4*(i0)) -#define VIVS_PS_HALTI5_UNK01080__ESIZE 0x00000004 -#define VIVS_PS_HALTI5_UNK01080__LEN 0x00000004 +#define VIVS_PS_NEWRANGE_LOW 0x0000087c -#define VIVS_PS_HALTI5_UNK01090 0x00001090 +#define VIVS_PS_NEWRANGE_HIGH 0x00001090 -#define VIVS_PS_HALTI5_UNK01094 0x00001094 +#define VIVS_PS_ICACHE_COUNT 0x00001094 #define VIVS_PS_HALTI5_UNK01098 0x00001098 @@ -686,6 +672,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GS_UNK01114 0x00001114 +#define VIVS_GS_ICACHE_PREFETCH 0x00001118 + #define VIVS_GS_UNK0111C 0x0000111c #define VIVS_GS_UNK01120(i0) (0x00001120 + 0x4*(i0)) @@ -712,6 +700,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_TCS_UNK14A08 0x00014a08 +#define VIVS_TCS_ICACHE_PREFETCH 0x00014a0c + #define VIVS_TCS_UNK14A10 0x00014a10 #define VIVS_TCS_UNK14A14 0x00014a14 @@ -740,6 +730,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_TES_UNK14B0C 0x00014b0c +#define VIVS_TES_ICACHE_PREFETCH 0x00014b10 + #define VIVS_TES_UNK14B14 0x00014b14 #define VIVS_TES_UNK14B18 0x00014b18 @@ -947,6 +939,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK 0x00000f00 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT 8 #define VIVS_PE_COLOR_FORMAT_COMPONENTS(x) (((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK) +#define VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW 0x00002000 #define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK 0x00001000 #define VIVS_PE_COLOR_FORMAT_OVERWRITE 0x00010000 #define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK 0x00020000 @@ -1046,7 +1039,13 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT 8 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK) -#define VIVS_PE_HALTI3_UNK014BC 0x000014bc +#define VIVS_PE_MEM_CONFIG 0x000014bc +#define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__MASK 0x01000000 +#define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__SHIFT 24 +#define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__MASK) +#define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__MASK 0x04000000 +#define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__SHIFT 26 +#define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__MASK) #define VIVS_PE_HALTI4_UNK014C0 0x000014c0 @@ -1270,14 +1269,10 @@ DEALINGS IN THE SOFTWARE. #define VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE 0x00000010 #define VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE 0x00000020 #define VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION 0x00000040 -#define VIVS_TS_MEM_CONFIG_MSAA 0x00000080 -#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT__MASK 0x00000f00 -#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT__SHIFT 8 -#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A4R4G4B4 0x00000000 -#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A1R5G5B5 0x00000100 -#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_R5G6B5 0x00000200 -#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8 0x00000300 -#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_X8R8G8B8 0x00000400 +#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION 0x00000080 +#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK 0x00000f00 +#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT 8 +#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK) #define VIVS_TS_MEM_CONFIG_UNK12 0x00001000 #define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE 0x00002000 #define VIVS_TS_MEM_CONFIG_UNK14 0x00004000 @@ -1419,6 +1414,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK 0x000ffc00 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK) +#define VIVS_TE_SAMPLER_LOG_SIZE_ASTC 0x10000000 #define VIVS_TE_SAMPLER_LOG_SIZE_RGB 0x20000000 #define VIVS_TE_SAMPLER_LOG_SIZE_SRGB 0x80000000 @@ -1450,7 +1446,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK) #define VIVS_TE_SAMPLER_CONFIG1(i0) (0x000021c0 + 0x4*(i0)) -#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000001f +#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000003f #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK) #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700 @@ -1465,6 +1461,9 @@ DEALINGS IN THE SOFTWARE. #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK) +#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__MASK 0x00800000 +#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT 23 +#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__MASK) #define VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000 #define VIVS_TE_SAMPLER_CONFIG1_UNK25 0x02000000 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000 @@ -1534,6 +1533,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK 0x000ffc00 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK) +#define VIVS_NTE_SAMPLER_LOG_SIZE_ASTC 0x10000000 #define VIVS_NTE_SAMPLER_LOG_SIZE_RGB 0x20000000 #define VIVS_NTE_SAMPLER_LOG_SIZE_SRGB 0x80000000 @@ -1553,10 +1553,19 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_SAMPLER_UNK10280(i0) (0x00010280 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_UNK10300(i0) (0x00010300 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_3D_CONFIG(i0) (0x00010300 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff +#define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT 0 +#define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK) +#define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK 0x03ff0000 +#define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT 16 +#define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK) +#define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK 0x30000000 +#define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT 28 +#define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK) #define VIVS_NTE_SAMPLER_CONFIG1(i0) (0x00010380 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000001f +#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000003f #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700 @@ -1571,6 +1580,9 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK) +#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__MASK 0x00800000 +#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT 23 +#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000 #define VIVS_NTE_SAMPLER_CONFIG1_UNK25 0x02000000 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000 @@ -1581,15 +1593,34 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_SAMPLER_UNK10480(i0) (0x00010480 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_ASTC_UNK10500(i0) (0x00010500 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_ASTC0(i0) (0x00010500 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x000000ff +#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT 0 +#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK) +#define VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK 0x0000ff00 +#define VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT 8 +#define VIVS_NTE_SAMPLER_ASTC0_UNK8(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK) +#define VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK 0x00ff0000 +#define VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT 16 +#define VIVS_NTE_SAMPLER_ASTC0_UNK16(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK) +#define VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK 0xff000000 +#define VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT 24 +#define VIVS_NTE_SAMPLER_ASTC0_UNK24(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK) -#define VIVS_NTE_SAMPLER_ASTC_UNK10580(i0) (0x00010580 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_ASTC1(i0) (0x00010580 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_ASTC_UNK10600(i0) (0x00010600 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_ASTC2(i0) (0x00010600 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_ASTC_UNK10680(i0) (0x00010600 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_ASTC3(i0) (0x00010600 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_BASELOD(i0) (0x00010700 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_BASELOD_UNK23 0x00800000 +#define VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK 0x0000000f +#define VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT 0 +#define VIVS_NTE_SAMPLER_BASELOD_BASELOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK) +#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK 0x00000f00 +#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT 8 +#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK) #define VIVS_NTE_SAMPLER_UNK10780(i0) (0x00010780 + 0x4*(i0)) @@ -1628,6 +1659,12 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_HALTI3_UNK14C00__LEN 0x00000010 #define VIVS_NTE_DESCRIPTOR_UNK14C40 0x00014c40 +#define VIVS_NTE_DESCRIPTOR_UNK14C40_UNK0 0x00000001 + +#define VIVS_NTE_DESCRIPTOR_FLUSH 0x00014c44 +#define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK 0xf0000000 +#define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT 28 +#define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28(x) (((x) << VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT) & VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK) #define VIVS_NTE_DESCRIPTOR_INVALIDATE 0x00014c48 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK 0x000001ff @@ -1639,36 +1676,83 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_DESCRIPTOR__ESIZE 0x00000004 #define VIVS_NTE_DESCRIPTOR__LEN 0x00000080 -#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK15C00(i0) (0x00015800 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK15E00(i0) (0x00015a00 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_UNK15C00(i0) (0x00015c00 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_UNK15E00(i0) (0x00015e00 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK16C00(i0) (0x00016000 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK16E00(i0) (0x00016200 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK17000(i0) (0x00016400 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK17200(i0) (0x00016600 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK17400(i0) (0x00016800 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_UNK16C00(i0) (0x00016c00 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_UNK16E00(i0) (0x00016e00 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_UNK17000(i0) (0x00017000 + 0x4*(i0)) - -#define VIVS_NTE_DESCRIPTOR_UNK17200(i0) (0x00017200 + 0x4*(i0)) +#define VIVS_NTE_DESCRIPTOR_ADDR_MIRROR(i0) (0x00015800 + 0x4*(i0)) + +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_MIRROR(i0) (0x00015a00 + 0x4*(i0)) + +#define VIVS_NTE_DESCRIPTOR_ADDR(i0) (0x00015c00 + 0x4*(i0)) + +#define VIVS_NTE_DESCRIPTOR_TX_CTRL(i0) (0x00015e00 + 0x4*(i0)) +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__MASK 0x00000003 +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__SHIFT 0 +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__MASK) +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK 0x0000001c +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT 2 +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK) + +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIRROR(i0) (0x00016000 + 0x4*(i0)) + +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_MIRROR(i0) (0x00016200 + 0x4*(i0)) + +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIRROR(i0) (0x00016400 + 0x4*(i0)) + +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_MIRROR(i0) (0x00016600 + 0x4*(i0)) + +#define VIVS_NTE_DESCRIPTOR_UNK17400_MIRROR(i0) (0x00016800 + 0x4*(i0)) + +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(i0) (0x00016c00 + 0x4*(i0)) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK 0x00000007 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT 0 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK 0x00000038 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT 3 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK 0x000001c0 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT 6 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK 0x00000600 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT 9 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK 0x00001800 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT 11 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK 0x00006000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT 13 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21 0x00200000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK22 0x00400000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_RGB 0x00800000 + +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(i0) (0x00016e00 + 0x4*(i0)) +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK1 0x00000002 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_SRGB 0x00000004 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK3 0x00000008 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK 0x00000030 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT 4 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK) + +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX(i0) (0x00017000 + 0x4*(i0)) +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK 0x0000ffff +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT 0 +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK 0xffff0000 +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT 16 +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK) + +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS(i0) (0x00017200 + 0x4*(i0)) +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK 0x0000ffff +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT 0 +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK) +#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE 0x00010000 #define VIVS_NTE_DESCRIPTOR_UNK17400(i0) (0x00017400 + 0x4*(i0)) #define VIVS_SH 0x00000000 +#define VIVS_SH_CONFIG 0x00015600 +#define VIVS_SH_CONFIG_RTNE_ROUNDING 0x00000002 +#define VIVS_SH_CONFIG_DUAL16 0x00000004 + #define VIVS_SH_UNK20000(i0) (0x00020000 + 0x4*(i0)) #define VIVS_SH_UNK20000__ESIZE 0x00000004 #define VIVS_SH_UNK20000__LEN 0x00002000 |