diff options
Diffstat (limited to 'src/gallium/drivers/etnaviv/etnaviv_state.c')
| -rw-r--r-- | src/gallium/drivers/etnaviv/etnaviv_state.c | 35 |
1 files changed, 25 insertions, 10 deletions
diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c b/src/gallium/drivers/etnaviv/etnaviv_state.c index 1e0b7548a48..b859f40c29f 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_state.c +++ b/src/gallium/drivers/etnaviv/etnaviv_state.c @@ -135,7 +135,8 @@ etna_set_framebuffer_state(struct pipe_context *pctx, VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) | VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK | VIVS_PE_COLOR_FORMAT_OVERWRITE | - COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED); + COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) | + COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW); /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state * but only if we set the bits above. */ @@ -211,7 +212,9 @@ etna_set_framebuffer_state(struct pipe_context *pctx, cs->PE_DEPTH_CONFIG = depth_format | COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) | - VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z; + VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z | + COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */ + ; /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */ /* merged with depth_stencil_alpha */ @@ -542,14 +545,26 @@ etna_vertex_elements_state_create(struct pipe_context *pctx, assert(format_type != ETNA_NO_MATCH); assert(normalize != ETNA_NO_MATCH); - cs->FE_VERTEX_ELEMENT_CONFIG[idx] = - COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) | - format_type | - VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) | - normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) | - VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) | - VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) | - VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset); + if (ctx->specs.halti < 5) { + cs->FE_VERTEX_ELEMENT_CONFIG[idx] = + COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) | + format_type | + VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) | + normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) | + VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) | + VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) | + VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset); + } else { /* HALTI5 spread vertex attrib config over two registers */ + cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] = + format_type | + VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) | + normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) | + VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(elements[idx].vertex_buffer_index) | + VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset); + cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] = + COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) | + VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset); + } cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 0x3f800000; /* 1 for integer, 1.0 for float */ } |