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diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 881aef6a797..5068285aaee 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -2082,6 +2082,246 @@ Perform a * b + c with no intermediate rounding step. dst.y = unsigned(src0.zw) +64-bit Integer ISA +^^^^^^^^^^^^^^^^^^ + +The 64-bit integer opcodes reinterpret four-component vectors into +two-component vectors with 64-bits in each component. + +.. opcode:: I64ABS - 64-bit Integer Absolute Value + + dst.xy = |src0.xy| + dst.zw = |src0.zw| + +.. opcode:: I64NEG - 64-bit Integer Negate + + Two's complement. + +.. math:: + + dst.xy = -src.xy + dst.zw = -src.zw + +.. opcode:: I64SSG - 64-bit Integer Set Sign + +.. math:: + + dst.xy = (src0.xy < 0) ? -1 : (src0.xy > 0) ? 1 : 0 + dst.zw = (src0.zw < 0) ? -1 : (src0.zw > 0) ? 1 : 0 + +.. opcode:: U64ADD - 64-bit Integer Add + +.. math:: + + dst.xy = src0.xy + src1.xy + dst.zw = src0.zw + src1.zw + +.. opcode:: U64MUL - 64-bit Integer Multiply + +.. math:: + + dst.xy = src0.xy * src1.xy + dst.zw = src0.zw * src1.zw + +.. opcode:: U64SEQ - 64-bit Integer Set on Equal + +.. math:: + + dst.x = src0.xy == src1.xy ? \sim 0 : 0 + dst.z = src0.zw == src1.zw ? \sim 0 : 0 + +.. opcode:: U64SNE - 64-bit Integer Set on Not Equal + +.. math:: + + dst.x = src0.xy != src1.xy ? \sim 0 : 0 + dst.z = src0.zw != src1.zw ? \sim 0 : 0 + +.. opcode:: U64SLT - 64-bit Unsigned Integer Set on Less Than + +.. math:: + + dst.x = src0.xy < src1.xy ? \sim 0 : 0 + dst.z = src0.zw < src1.zw ? \sim 0 : 0 + +.. opcode:: U64SGE - 64-bit Unsigned Integer Set on Greater Equal + +.. math:: + + dst.x = src0.xy >= src1.xy ? \sim 0 : 0 + dst.z = src0.zw >= src1.zw ? \sim 0 : 0 + +.. opcode:: I64SLT - 64-bit Signed Integer Set on Less Than + +.. math:: + + dst.x = src0.xy < src1.xy ? \sim 0 : 0 + dst.z = src0.zw < src1.zw ? \sim 0 : 0 + +.. opcode:: I64SGE - 64-bit Signed Integer Set on Greater Equal + +.. math:: + + dst.x = src0.xy >= src1.xy ? \sim 0 : 0 + dst.z = src0.zw >= src1.zw ? \sim 0 : 0 + +.. opcode:: I64MIN - Minimum of 64-bit Signed Integers + +.. math:: + + dst.xy = min(src0.xy, src1.xy) + dst.zw = min(src0.zw, src1.zw) + +.. opcode:: U64MIN - Minimum of 64-bit Unsigned Integers + +.. math:: + + dst.xy = min(src0.xy, src1.xy) + dst.zw = min(src0.zw, src1.zw) + +.. opcode:: I64MAX - Maximum of 64-bit Signed Integers + +.. math:: + + dst.xy = max(src0.xy, src1.xy) + dst.zw = max(src0.zw, src1.zw) + +.. opcode:: U64MAX - Maximum of 64-bit Unsigned Integers + +.. math:: + + dst.xy = max(src0.xy, src1.xy) + dst.zw = max(src0.zw, src1.zw) + +.. opcode:: U64SHL - Shift Left 64-bit Unsigned Integer + + The shift count is masked with 0x3f before the shift is applied. + +.. math:: + + dst.xy = src0.xy << (0x3f \& src1.x) + dst.zw = src0.zw << (0x3f \& src1.y) + +.. opcode:: I64SHR - Arithmetic Shift Right (of 64-bit Signed Integer) + + The shift count is masked with 0x3f before the shift is applied. + +.. math:: + + dst.xy = src0.xy >> (0x3f \& src1.x) + dst.zw = src0.zw >> (0x3f \& src1.y) + +.. opcode:: U64SHR - Logical Shift Right (of 64-bit Unsigned Integer) + + The shift count is masked with 0x3f before the shift is applied. + +.. math:: + + dst.xy = src0.xy >> (unsigned) (0x3f \& src1.x) + dst.zw = src0.zw >> (unsigned) (0x3f \& src1.y) + +.. opcode:: I64DIV - 64-bit Signed Integer Division + +.. math:: + + dst.xy = src0.xy \ src1.xy + dst.zw = src0.zw \ src1.zw + +.. opcode:: U64DIV - 64-bit Unsigned Integer Division + +.. math:: + + dst.xy = src0.xy \ src1.xy + dst.zw = src0.zw \ src1.zw + +.. opcode:: U64MOD - 64-bit Unsigned Integer Remainder + +.. math:: + + dst.xy = src0.xy \bmod src1.xy + dst.zw = src0.zw \bmod src1.zw + +.. opcode:: I64MOD - 64-bit Signed Integer Remainder + +.. math:: + + dst.xy = src0.xy \bmod src1.xy + dst.zw = src0.zw \bmod src1.zw + +.. opcode:: F2U64 - Float to 64-bit Unsigned Int + +.. math:: + + dst.xy = (uint64_t) src0.x + dst.zw = (uint64_t) src0.y + +.. opcode:: F2I64 - Float to 64-bit Int + +.. math:: + + dst.xy = (int64_t) src0.x + dst.zw = (int64_t) src0.y + +.. opcode:: U2I64 - Unsigned Integer to 64-bit Integer + + This is a zero extension. + +.. math:: + + dst.xy = (uint64_t) src0.x + dst.zw = (uint64_t) src0.y + +.. opcode:: I2I64 - Signed Integer to 64-bit Integer + + This is a sign extension. + +.. math:: + + dst.xy = (int64_t) src0.x + dst.zw = (int64_t) src0.y + +.. opcode:: D2U64 - Double to 64-bit Unsigned Int + +.. math:: + + dst.xy = (uint64_t) src0.xy + dst.zw = (uint64_t) src0.zw + +.. opcode:: D2I64 - Double to 64-bit Int + +.. math:: + + dst.xy = (int64_t) src0.xy + dst.zw = (int64_t) src0.zw + +.. opcode:: U642F - 64-bit unsigned integer to float + +.. math:: + + dst.x = (float) src0.xy + dst.y = (float) src0.zw + +.. opcode:: I642F - 64-bit Int to Float + +.. math:: + + dst.x = (float) src0.xy + dst.y = (float) src0.zw + +.. opcode:: U642D - 64-bit unsigned integer to double + +.. math:: + + dst.xy = (double) src0.xy + dst.zw = (double) src0.zw + +.. opcode:: I642D - 64-bit Int to double + +.. math:: + + dst.xy = (double) src0.xy + dst.zw = (double) src0.zw + .. _samplingopcodes: Resource Sampling Opcodes |