1 files changed, 22 insertions, 2 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_sanity.c b/src/gallium/auxiliary/tgsi/tgsi_sanity.c
index 8bb186bae54..cb62a95fc0a 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_sanity.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_sanity.c
@@ -235,9 +235,29 @@ iter_instruction(
             index,
             "indirect",
             FALSE );
-         if (file != TGSI_FILE_ADDRESS || index != 0)
-            report_warning( ctx, "Indirect register not ADDR[0]" );
+         if (!(file == TGSI_FILE_ADDRESS || file == TGSI_FILE_LOOP) || index != 0) {
+            report_warning(ctx, "Indirect register neither ADDR[0] nor LOOP[0]");
+         }
+      }
+   }
+
+   switch (inst->Instruction.Opcode) {
+   case TGSI_OPCODE_LOOP:
+   case TGSI_OPCODE_ENDLOOP:
+      if (inst->FullDstRegisters[0].DstRegister.File != TGSI_FILE_LOOP ||
+          inst->FullDstRegisters[0].DstRegister.Index != 0) {
+         report_error(ctx, "Destination register must be LOOP[0]");
+      }
+      break;
+   }
+
+   switch (inst->Instruction.Opcode) {
+   case TGSI_OPCODE_LOOP:
+      if (inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_CONSTANT &&
+          inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_IMMEDIATE) {
+         report_error(ctx, "Source register file must be either CONST or IMM");
       }
+      break;
    }
 
    ctx->num_instructions++;