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-rw-r--r--src/freedreno/ir3/ir3_cp.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/freedreno/ir3/ir3_cp.c b/src/freedreno/ir3/ir3_cp.c
index efcefaeb2b2..03bb8cbe091 100644
--- a/src/freedreno/ir3/ir3_cp.c
+++ b/src/freedreno/ir3/ir3_cp.c
@@ -523,6 +523,17 @@ reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
(src_reg->array.offset == 0))
return false;
+ /* When narrowing constant from 32b to 16b, it seems
+ * to work only for float. So we should do this only with
+ * float opcodes.
+ */
+ if (src->cat1.dst_type == TYPE_F16) {
+ if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
+ return false;
+ if (!ir3_cat2_float(instr->opc) && !ir3_cat3_float(instr->opc))
+ return false;
+ }
+
src_reg = ir3_reg_clone(instr->block->shader, src_reg);
src_reg->flags = new_flags;
instr->regs[n+1] = src_reg;