1 files changed, 18 insertions, 35 deletions

diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c
index 8c7d9a33f3a..d2210184a60 100644
--- a/src/freedreno/ir3/ir3_context.c
+++ b/src/freedreno/ir3/ir3_context.c
@@ -101,51 +101,34 @@ ir3_context_init(struct ir3_compiler *compiler,
 		nir_print_shader(ctx->s, stderr);
 	}
 
-	ir3_nir_scan_driver_consts(ctx->s, &so->const_layout);
+	ir3_ibo_mapping_init(&so->image_mapping, ctx->s->info.num_textures);
 
-	so->num_uniforms = ctx->s->num_uniforms;
-	so->num_ubos = ctx->s->info.num_ubos;
+	struct ir3_const_state *const_state = &so->const_state;
+	memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 
-	ir3_ibo_mapping_init(&so->image_mapping, ctx->s->info.num_textures);
+	ir3_nir_scan_driver_consts(ctx->s, const_state);
+
+	const_state->num_uniforms = ctx->s->num_uniforms;
+	const_state->num_ubos = ctx->s->info.num_ubos;
 
-	/* Layout of constant registers, each section aligned to vec4.  Note
-	 * that pointer size (ubo, etc) changes depending on generation.
-	 *
-	 *    user consts
-	 *    UBO addresses
-	 *    SSBO sizes
-	 *    if (vertex shader) {
-	 *        driver params (IR3_DP_*)
-	 *        if (stream_output.num_outputs > 0)
-	 *           stream-out addresses
-	 *    }
-	 *    immediates
-	 *
-	 * Immediates go last mostly because they are inserted in the CP pass
-	 * after the nir -> ir3 frontend.
-	 *
-	 * Note UBO size in bytes should be aligned to vec4
-	 */
 	debug_assert((ctx->so->shader->ubo_state.size % 16) == 0);
 	unsigned constoff = align(ctx->so->shader->ubo_state.size / 16, 4);
 	unsigned ptrsz = ir3_pointer_size(ctx->compiler);
 
-	memset(&so->constbase, ~0, sizeof(so->constbase));
-
-	if (so->num_ubos > 0) {
-		so->constbase.ubo = constoff;
+	if (const_state->num_ubos > 0) {
+		const_state->offsets.ubo = constoff;
 		constoff += align(ctx->s->info.num_ubos * ptrsz, 4) / 4;
 	}
 
-	if (so->const_layout.ssbo_size.count > 0) {
-		unsigned cnt = so->const_layout.ssbo_size.count;
-		so->constbase.ssbo_sizes = constoff;
+	if (const_state->ssbo_size.count > 0) {
+		unsigned cnt = const_state->ssbo_size.count;
+		const_state->offsets.ssbo_sizes = constoff;
 		constoff += align(cnt, 4) / 4;
 	}
 
-	if (so->const_layout.image_dims.count > 0) {
-		unsigned cnt = so->const_layout.image_dims.count;
-		so->constbase.image_dims = constoff;
+	if (const_state->image_dims.count > 0) {
+		unsigned cnt = const_state->image_dims.count;
+		const_state->offsets.image_dims = constoff;
 		constoff += align(cnt, 4) / 4;
 	}
 
@@ -156,17 +139,17 @@ ir3_context_init(struct ir3_compiler *compiler,
 		num_driver_params = IR3_DP_CS_COUNT;
 	}
 
-	so->constbase.driver_param = constoff;
+	const_state->offsets.driver_param = constoff;
 	constoff += align(num_driver_params, 4) / 4;
 
 	if ((so->type == MESA_SHADER_VERTEX) &&
 			(compiler->gpu_id < 500) &&
 			so->shader->stream_output.num_outputs > 0) {
-		so->constbase.tfbo = constoff;
+		const_state->offsets.tfbo = constoff;
 		constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 	}
 
-	so->constbase.immediate = constoff;
+	const_state->offsets.immediate = constoff;
 
 	return ctx;
 }