diff options
Diffstat (limited to 'src/compiler')
| -rw-r--r-- | src/compiler/nir/nir.h | 20 | ||||
| -rw-r--r-- | src/compiler/nir/nir_algebraic.py | 30 | ||||
| -rw-r--r-- | src/compiler/nir/nir_builder_opcodes_h.py | 39 | ||||
| -rw-r--r-- | src/compiler/nir/nir_loop_analyze.c | 28 | ||||
| -rw-r--r-- | src/compiler/nir/nir_lower_alu_to_scalar.c | 8 | ||||
| -rw-r--r-- | src/compiler/nir/nir_opcodes.py | 34 | ||||
| -rw-r--r-- | src/compiler/nir/nir_opt_if.c | 2 | ||||
| -rw-r--r-- | src/compiler/nir/nir_opt_peephole_select.c | 2 | ||||
| -rw-r--r-- | src/compiler/nir/nir_opt_undef.c | 2 | ||||
| -rw-r--r-- | src/compiler/spirv/vtn_alu.c | 62 |
10 files changed, 147 insertions, 80 deletions
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index aae8e83db7a..d16eabdec53 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1559,16 +1559,16 @@ static inline bool nir_alu_instr_is_comparison(const nir_alu_instr *instr) { switch (instr->op) { - case nir_op_flt: - case nir_op_fge: - case nir_op_feq: - case nir_op_fne: - case nir_op_ilt: - case nir_op_ult: - case nir_op_ige: - case nir_op_uge: - case nir_op_ieq: - case nir_op_ine: + case nir_op_flt32: + case nir_op_fge32: + case nir_op_feq32: + case nir_op_fne32: + case nir_op_ilt32: + case nir_op_ult32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ieq32: + case nir_op_ine32: case nir_op_i2b32: case nir_op_f2b32: case nir_op_inot: diff --git a/src/compiler/nir/nir_algebraic.py b/src/compiler/nir/nir_algebraic.py index c16cadbdc58..9a28421b799 100644 --- a/src/compiler/nir/nir_algebraic.py +++ b/src/compiler/nir/nir_algebraic.py @@ -277,6 +277,34 @@ class Variable(Value): _opcode_re = re.compile(r"(?P<inexact>~)?(?P<opcode>\w+)(?:@(?P<bits>\d+))?" r"(?P<cond>\([^\)]+\))?") +opcode_remap = { + 'flt' : 'flt32', + 'fge' : 'fge32', + 'feq' : 'feq32', + 'fne' : 'fne32', + 'ilt' : 'ilt32', + 'ige' : 'ige32', + 'ieq' : 'ieq32', + 'ine' : 'ine32', + 'ult' : 'ult32', + 'uge' : 'uge32', + + 'ball_iequal2' : 'b32all_iequal2', + 'ball_iequal3' : 'b32all_iequal3', + 'ball_iequal4' : 'b32all_iequal4', + 'bany_inequal2' : 'b32any_inequal2', + 'bany_inequal3' : 'b32any_inequal3', + 'bany_inequal4' : 'b32any_inequal4', + 'ball_fequal2' : 'b32all_fequal2', + 'ball_fequal3' : 'b32all_fequal3', + 'ball_fequal4' : 'b32all_fequal4', + 'bany_fnequal2' : 'b32any_fnequal2', + 'bany_fnequal3' : 'b32any_fnequal3', + 'bany_fnequal4' : 'b32any_fnequal4', + + 'bcsel' : 'b32csel', +} + class Expression(Value): def __init__(self, expr, name_base, varset): Value.__init__(self, expr, name_base, "expression") @@ -286,6 +314,8 @@ class Expression(Value): assert m and m.group('opcode') is not None self.opcode = m.group('opcode') + if self.opcode in opcode_remap: + self.opcode = opcode_remap[self.opcode] self._bit_size = int(m.group('bits')) if m.group('bits') else None self.inexact = m.group('inexact') is not None self.cond = m.group('cond') diff --git a/src/compiler/nir/nir_builder_opcodes_h.py b/src/compiler/nir/nir_builder_opcodes_h.py index 34b8c4371e1..5c38818d4ec 100644 --- a/src/compiler/nir/nir_builder_opcodes_h.py +++ b/src/compiler/nir/nir_builder_opcodes_h.py @@ -27,6 +27,36 @@ template = """\ #define _NIR_BUILDER_OPCODES_ <% +opcode_remap = { + 'flt' : 'flt32', + 'fge' : 'fge32', + 'feq' : 'feq32', + 'fne' : 'fne32', + 'ilt' : 'ilt32', + 'ige' : 'ige32', + 'ieq' : 'ieq32', + 'ine' : 'ine32', + 'ult' : 'ult32', + 'uge' : 'uge32', + + 'ball_iequal2' : 'b32all_iequal2', + 'ball_iequal3' : 'b32all_iequal3', + 'ball_iequal4' : 'b32all_iequal4', + 'bany_inequal2' : 'b32any_inequal2', + 'bany_inequal3' : 'b32any_inequal3', + 'bany_inequal4' : 'b32any_inequal4', + 'ball_fequal2' : 'b32all_fequal2', + 'ball_fequal3' : 'b32all_fequal3', + 'ball_fequal4' : 'b32all_fequal4', + 'bany_fnequal2' : 'b32any_fnequal2', + 'bany_fnequal3' : 'b32any_fnequal3', + 'bany_fnequal4' : 'b32any_fnequal4', + + 'bcsel' : 'b32csel', +} + +opcode_remap32 = { op32 : op for op, op32 in opcode_remap.items() } + def src_decl_list(num_srcs): return ', '.join('nir_ssa_def *src' + str(i) for i in range(num_srcs)) @@ -35,8 +65,15 @@ def src_list(num_srcs): %> % for name, opcode in sorted(opcodes.items()): + % if name in opcode_remap: + <% continue %> + % elif name in opcode_remap32: + <% builder_name = opcode_remap32[name] %> + % else: + <% builder_name = name %> + % endif static inline nir_ssa_def * -nir_${name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)}) +nir_${builder_name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)}) { return nir_build_alu(build, nir_op_${name}, ${src_list(opcode.num_inputs)}); } diff --git a/src/compiler/nir/nir_loop_analyze.c b/src/compiler/nir/nir_loop_analyze.c index 259f02a854e..a82a5113b5e 100644 --- a/src/compiler/nir/nir_loop_analyze.c +++ b/src/compiler/nir/nir_loop_analyze.c @@ -433,26 +433,26 @@ get_iteration(nir_op cond_op, nir_const_value *initial, nir_const_value *step, int32_t iter; switch (cond_op) { - case nir_op_ige: - case nir_op_ilt: - case nir_op_ieq: - case nir_op_ine: { + case nir_op_ige32: + case nir_op_ilt32: + case nir_op_ieq32: + case nir_op_ine32: { int32_t initial_val = initial->i32[0]; int32_t span = limit->i32[0] - initial_val; iter = span / step->i32[0]; break; } - case nir_op_uge: - case nir_op_ult: { + case nir_op_uge32: + case nir_op_ult32: { uint32_t initial_val = initial->u32[0]; uint32_t span = limit->u32[0] - initial_val; iter = span / step->u32[0]; break; } - case nir_op_fge: - case nir_op_flt: - case nir_op_feq: - case nir_op_fne: { + case nir_op_fge32: + case nir_op_flt32: + case nir_op_feq32: + case nir_op_fne32: { float initial_val = initial->f32[0]; float span = limit->f32[0] - initial_val; iter = span / step->f32[0]; @@ -623,10 +623,10 @@ find_trip_count(loop_info_state *state) bool limit_rhs = true; switch (alu->op) { - case nir_op_fge: case nir_op_ige: case nir_op_uge: - case nir_op_flt: case nir_op_ilt: case nir_op_ult: - case nir_op_feq: case nir_op_ieq: - case nir_op_fne: case nir_op_ine: + case nir_op_fge32: case nir_op_ige32: case nir_op_uge32: + case nir_op_flt32: case nir_op_ilt32: case nir_op_ult32: + case nir_op_feq32: case nir_op_ieq32: + case nir_op_fne32: case nir_op_ine32: /* We assume that the limit is the "right" operand */ basic_ind = get_loop_var(alu->src[0].src.ssa, state); diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c b/src/compiler/nir/nir_lower_alu_to_scalar.c index 7ef032cd164..e406207c3cd 100644 --- a/src/compiler/nir/nir_lower_alu_to_scalar.c +++ b/src/compiler/nir/nir_lower_alu_to_scalar.c @@ -198,10 +198,10 @@ lower_alu_instr_scalar(nir_alu_instr *instr, nir_builder *b) return false; LOWER_REDUCTION(nir_op_fdot, nir_op_fmul, nir_op_fadd); - LOWER_REDUCTION(nir_op_ball_fequal, nir_op_feq, nir_op_iand); - LOWER_REDUCTION(nir_op_ball_iequal, nir_op_ieq, nir_op_iand); - LOWER_REDUCTION(nir_op_bany_fnequal, nir_op_fne, nir_op_ior); - LOWER_REDUCTION(nir_op_bany_inequal, nir_op_ine, nir_op_ior); + LOWER_REDUCTION(nir_op_b32all_fequal, nir_op_feq32, nir_op_iand); + LOWER_REDUCTION(nir_op_b32all_iequal, nir_op_ieq32, nir_op_iand); + LOWER_REDUCTION(nir_op_b32any_fnequal, nir_op_fne32, nir_op_ior); + LOWER_REDUCTION(nir_op_b32any_inequal, nir_op_ine32, nir_op_ior); LOWER_REDUCTION(nir_op_fall_equal, nir_op_seq, nir_op_fand); LOWER_REDUCTION(nir_op_fany_nequal, nir_op_sne, nir_op_for); diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 5458ddd8198..c89bdeb436a 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/nir_opcodes.py @@ -430,7 +430,7 @@ def binop_convert(name, out_type, in_type, alg_props, const_expr): def binop(name, ty, alg_props, const_expr): binop_convert(name, ty, ty, alg_props, const_expr) -def binop_compare(name, ty, alg_props, const_expr): +def binop_compare32(name, ty, alg_props, const_expr): binop_convert(name, tbool32, ty, alg_props, const_expr) def binop_horiz(name, out_size, out_type, src1_size, src1_type, src2_size, @@ -550,26 +550,26 @@ binop("frem", tfloat, "", "src0 - src1 * truncf(src0 / src1)") # these integer-aware comparisons return a boolean (0 or ~0) -binop_compare("flt", tfloat, "", "src0 < src1") -binop_compare("fge", tfloat, "", "src0 >= src1") -binop_compare("feq", tfloat, commutative, "src0 == src1") -binop_compare("fne", tfloat, commutative, "src0 != src1") -binop_compare("ilt", tint, "", "src0 < src1") -binop_compare("ige", tint, "", "src0 >= src1") -binop_compare("ieq", tint, commutative, "src0 == src1") -binop_compare("ine", tint, commutative, "src0 != src1") -binop_compare("ult", tuint, "", "src0 < src1") -binop_compare("uge", tuint, "", "src0 >= src1") +binop_compare32("flt32", tfloat, "", "src0 < src1") +binop_compare32("fge32", tfloat, "", "src0 >= src1") +binop_compare32("feq32", tfloat, commutative, "src0 == src1") +binop_compare32("fne32", tfloat, commutative, "src0 != src1") +binop_compare32("ilt32", tint, "", "src0 < src1") +binop_compare32("ige32", tint, "", "src0 >= src1") +binop_compare32("ieq32", tint, commutative, "src0 == src1") +binop_compare32("ine32", tint, commutative, "src0 != src1") +binop_compare32("ult32", tuint, "", "src0 < src1") +binop_compare32("uge32", tuint, "", "src0 >= src1") # integer-aware GLSL-style comparisons that compare floats and ints -binop_reduce("ball_fequal", 1, tbool32, tfloat, "{src0} == {src1}", +binop_reduce("b32all_fequal", 1, tbool32, tfloat, "{src0} == {src1}", "{src0} && {src1}", "{src}") -binop_reduce("bany_fnequal", 1, tbool32, tfloat, "{src0} != {src1}", +binop_reduce("b32any_fnequal", 1, tbool32, tfloat, "{src0} != {src1}", "{src0} || {src1}", "{src}") -binop_reduce("ball_iequal", 1, tbool32, tint, "{src0} == {src1}", +binop_reduce("b32all_iequal", 1, tbool32, tint, "{src0} == {src1}", "{src0} && {src1}", "{src}") -binop_reduce("bany_inequal", 1, tbool32, tint, "{src0} != {src1}", +binop_reduce("b32any_inequal", 1, tbool32, tint, "{src0} != {src1}", "{src0} || {src1}", "{src}") # non-integer-aware GLSL-style comparisons that return 0.0 or 1.0 @@ -756,8 +756,8 @@ triop("fmed3", tfloat, "fmaxf(fminf(fmaxf(src0, src1), src2), fminf(src0, src1)) triop("imed3", tint, "MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1))") triop("umed3", tuint, "MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1))") -opcode("bcsel", 0, tuint, [0, 0, 0], - [tbool32, tuint, tuint], "", "src0 ? src1 : src2") +opcode("b32csel", 0, tuint, [0, 0, 0], + [tbool32, tuint, tuint], "", "src0 ? src1 : src2") # SM5 bfi assembly triop("bfi", tuint32, """ diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index c21ac9219f0..f5951271e0d 100644 --- a/src/compiler/nir/nir_opt_if.c +++ b/src/compiler/nir/nir_opt_if.c @@ -609,7 +609,7 @@ can_propagate_through_alu(nir_src *src) case nir_op_inot: case nir_op_b2i32: return true; - case nir_op_bcsel: + case nir_op_b32csel: return src == &alu->src[0].src; default: return false; diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index ad9d0abec03..6308c8cab12 100644 --- a/src/compiler/nir/nir_opt_peephole_select.c +++ b/src/compiler/nir/nir_opt_peephole_select.c @@ -205,7 +205,7 @@ nir_opt_peephole_select_block(nir_block *block, nir_shader *shader, break; nir_phi_instr *phi = nir_instr_as_phi(instr); - nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_bcsel); + nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_b32csel); nir_src_copy(&sel->src[0].src, &if_stmt->condition, sel); /* Splat the condition to all channels */ memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle); diff --git a/src/compiler/nir/nir_opt_undef.c b/src/compiler/nir/nir_opt_undef.c index c26158dab7e..52c1d257e9f 100644 --- a/src/compiler/nir/nir_opt_undef.c +++ b/src/compiler/nir/nir_opt_undef.c @@ -38,7 +38,7 @@ static bool opt_undef_csel(nir_alu_instr *instr) { - if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel) + if (instr->op != nir_op_b32csel && instr->op != nir_op_fcsel) return false; assert(instr->dest.dest.is_ssa); diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index dc6fedc9129..b04ada92199 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -244,15 +244,15 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, case SpvOpShiftRightArithmetic: return nir_op_ishr; case SpvOpShiftLeftLogical: return nir_op_ishl; case SpvOpLogicalOr: return nir_op_ior; - case SpvOpLogicalEqual: return nir_op_ieq; - case SpvOpLogicalNotEqual: return nir_op_ine; + case SpvOpLogicalEqual: return nir_op_ieq32; + case SpvOpLogicalNotEqual: return nir_op_ine32; case SpvOpLogicalAnd: return nir_op_iand; case SpvOpLogicalNot: return nir_op_inot; case SpvOpBitwiseOr: return nir_op_ior; case SpvOpBitwiseXor: return nir_op_ixor; case SpvOpBitwiseAnd: return nir_op_iand; - case SpvOpSelect: return nir_op_bcsel; - case SpvOpIEqual: return nir_op_ieq; + case SpvOpSelect: return nir_op_b32csel; + case SpvOpIEqual: return nir_op_ieq32; case SpvOpBitFieldInsert: return nir_op_bitfield_insert; case SpvOpBitFieldSExtract: return nir_op_ibitfield_extract; @@ -264,27 +264,27 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, * the logical operator to use since they also need to check if operands are * ordered. */ - case SpvOpFOrdEqual: return nir_op_feq; - case SpvOpFUnordEqual: return nir_op_feq; - case SpvOpINotEqual: return nir_op_ine; - case SpvOpFOrdNotEqual: return nir_op_fne; - case SpvOpFUnordNotEqual: return nir_op_fne; - case SpvOpULessThan: return nir_op_ult; - case SpvOpSLessThan: return nir_op_ilt; - case SpvOpFOrdLessThan: return nir_op_flt; - case SpvOpFUnordLessThan: return nir_op_flt; - case SpvOpUGreaterThan: *swap = true; return nir_op_ult; - case SpvOpSGreaterThan: *swap = true; return nir_op_ilt; - case SpvOpFOrdGreaterThan: *swap = true; return nir_op_flt; - case SpvOpFUnordGreaterThan: *swap = true; return nir_op_flt; - case SpvOpULessThanEqual: *swap = true; return nir_op_uge; - case SpvOpSLessThanEqual: *swap = true; return nir_op_ige; - case SpvOpFOrdLessThanEqual: *swap = true; return nir_op_fge; - case SpvOpFUnordLessThanEqual: *swap = true; return nir_op_fge; - case SpvOpUGreaterThanEqual: return nir_op_uge; - case SpvOpSGreaterThanEqual: return nir_op_ige; - case SpvOpFOrdGreaterThanEqual: return nir_op_fge; - case SpvOpFUnordGreaterThanEqual: return nir_op_fge; + case SpvOpFOrdEqual: return nir_op_feq32; + case SpvOpFUnordEqual: return nir_op_feq32; + case SpvOpINotEqual: return nir_op_ine32; + case SpvOpFOrdNotEqual: return nir_op_fne32; + case SpvOpFUnordNotEqual: return nir_op_fne32; + case SpvOpULessThan: return nir_op_ult32; + case SpvOpSLessThan: return nir_op_ilt32; + case SpvOpFOrdLessThan: return nir_op_flt32; + case SpvOpFUnordLessThan: return nir_op_flt32; + case SpvOpUGreaterThan: *swap = true; return nir_op_ult32; + case SpvOpSGreaterThan: *swap = true; return nir_op_ilt32; + case SpvOpFOrdGreaterThan: *swap = true; return nir_op_flt32; + case SpvOpFUnordGreaterThan: *swap = true; return nir_op_flt32; + case SpvOpULessThanEqual: *swap = true; return nir_op_uge32; + case SpvOpSLessThanEqual: *swap = true; return nir_op_ige32; + case SpvOpFOrdLessThanEqual: *swap = true; return nir_op_fge32; + case SpvOpFUnordLessThanEqual: *swap = true; return nir_op_fge32; + case SpvOpUGreaterThanEqual: return nir_op_uge32; + case SpvOpSGreaterThanEqual: return nir_op_ige32; + case SpvOpFOrdGreaterThanEqual: return nir_op_fge32; + case SpvOpFUnordGreaterThanEqual: return nir_op_fge32; /* Conversions: */ case SpvOpQuantizeToF16: return nir_op_fquantize2f16; @@ -413,9 +413,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, } else { nir_op op; switch (src[0]->num_components) { - case 2: op = nir_op_bany_inequal2; break; - case 3: op = nir_op_bany_inequal3; break; - case 4: op = nir_op_bany_inequal4; break; + case 2: op = nir_op_b32any_inequal2; break; + case 3: op = nir_op_b32any_inequal3; break; + case 4: op = nir_op_b32any_inequal4; break; default: vtn_fail("invalid number of components"); } val->ssa->def = nir_build_alu(&b->nb, op, src[0], @@ -430,9 +430,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, } else { nir_op op; switch (src[0]->num_components) { - case 2: op = nir_op_ball_iequal2; break; - case 3: op = nir_op_ball_iequal3; break; - case 4: op = nir_op_ball_iequal4; break; + case 2: op = nir_op_b32all_iequal2; break; + case 3: op = nir_op_b32all_iequal3; break; + case 4: op = nir_op_b32all_iequal4; break; default: vtn_fail("invalid number of components"); } val->ssa->def = nir_build_alu(&b->nb, op, src[0], |