diff options
Diffstat (limited to 'src/broadcom')
| -rw-r--r-- | src/broadcom/qpu/qpu_instr.c | 31 | ||||
| -rw-r--r-- | src/broadcom/qpu/qpu_instr.h | 16 |
2 files changed, 37 insertions, 10 deletions
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c index 85d6cf75d81..986097a11be 100644 --- a/src/broadcom/qpu/qpu_instr.c +++ b/src/broadcom/qpu/qpu_instr.c @@ -54,6 +54,22 @@ v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr) [V3D_QPU_WADDR_LOG] = "log", [V3D_QPU_WADDR_SIN] = "sin", [V3D_QPU_WADDR_RSQRT2] = "rsqrt2", + [V3D_QPU_WADDR_TMUC] = "tmuc", + [V3D_QPU_WADDR_TMUS] = "tmus", + [V3D_QPU_WADDR_TMUT] = "tmut", + [V3D_QPU_WADDR_TMUR] = "tmur", + [V3D_QPU_WADDR_TMUI] = "tmui", + [V3D_QPU_WADDR_TMUB] = "tmub", + [V3D_QPU_WADDR_TMUDREF] = "tmudref", + [V3D_QPU_WADDR_TMUOFF] = "tmuoff", + [V3D_QPU_WADDR_TMUSCM] = "tmuscm", + [V3D_QPU_WADDR_TMUSF] = "tmusf", + [V3D_QPU_WADDR_TMUSLOD] = "tmuslod", + [V3D_QPU_WADDR_TMUHS] = "tmuhs", + [V3D_QPU_WADDR_TMUHSCM] = "tmuscm", + [V3D_QPU_WADDR_TMUHSF] = "tmuhsf", + [V3D_QPU_WADDR_TMUHSLOD] = "tmuhslod", + [V3D_QPU_WADDR_R5REP] = "r5rep", }; return waddr_magic[waddr]; @@ -489,16 +505,11 @@ v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr) bool v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr) { - switch (waddr) { - case V3D_QPU_WADDR_TMU: - case V3D_QPU_WADDR_TMUL: - case V3D_QPU_WADDR_TMUD: - case V3D_QPU_WADDR_TMUA: - case V3D_QPU_WADDR_TMUAU: - return true; - default: - return false; - } + /* XXX: WADDR_TMU changed to UNIFA on 4.x */ + return ((waddr >= V3D_QPU_WADDR_TMU && + waddr <= V3D_QPU_WADDR_TMUAU) || + (waddr >= V3D_QPU_WADDR_TMUC && + waddr <= V3D_QPU_WADDR_TMUHSLOD)); } bool diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h index 0bd79ca68da..b65a35ae3c3 100644 --- a/src/broadcom/qpu/qpu_instr.h +++ b/src/broadcom/qpu/qpu_instr.h @@ -114,6 +114,22 @@ enum v3d_qpu_waddr { V3D_QPU_WADDR_LOG = 22, V3D_QPU_WADDR_SIN = 23, V3D_QPU_WADDR_RSQRT2 = 24, + V3D_QPU_WADDR_TMUC = 32, + V3D_QPU_WADDR_TMUS = 33, + V3D_QPU_WADDR_TMUT = 34, + V3D_QPU_WADDR_TMUR = 35, + V3D_QPU_WADDR_TMUI = 36, + V3D_QPU_WADDR_TMUB = 37, + V3D_QPU_WADDR_TMUDREF = 38, + V3D_QPU_WADDR_TMUOFF = 39, + V3D_QPU_WADDR_TMUSCM = 40, + V3D_QPU_WADDR_TMUSF = 41, + V3D_QPU_WADDR_TMUSLOD = 42, + V3D_QPU_WADDR_TMUHS = 43, + V3D_QPU_WADDR_TMUHSCM = 44, + V3D_QPU_WADDR_TMUHSF = 45, + V3D_QPU_WADDR_TMUHSLOD = 46, + V3D_QPU_WADDR_R5REP = 55, }; struct v3d_qpu_flags { |