diff options
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/addrlib/amdgpu_asic_addr.h | 2 | ||||
| -rw-r--r-- | src/amd/addrlib/gfx9/gfx9addrlib.cpp | 2 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 6 | ||||
| -rw-r--r-- | src/amd/common/ac_llvm_util.c | 2 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.c | 4 | ||||
| -rw-r--r-- | src/amd/common/amd_family.h | 1 | ||||
| -rw-r--r-- | src/amd/common/gfx9d.h | 3 |
7 files changed, 19 insertions, 1 deletions
diff --git a/src/amd/addrlib/amdgpu_asic_addr.h b/src/amd/addrlib/amdgpu_asic_addr.h index e5838d42a3c..7436c5493e1 100644 --- a/src/amd/addrlib/amdgpu_asic_addr.h +++ b/src/amd/addrlib/amdgpu_asic_addr.h @@ -90,6 +90,7 @@ #define AMDGPU_VEGA20_RANGE 0x28, 0xFF #define AMDGPU_RAVEN_RANGE 0x01, 0x81 +#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF #define AMDGPU_EXPAND_FIX(x) x #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max)) @@ -132,5 +133,6 @@ #define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20) #define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN) +#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2) #endif // _AMDGPU_ASIC_ADDR_H diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp b/src/amd/addrlib/gfx9/gfx9addrlib.cpp index d27aabbb60c..f115242c89c 100644 --- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp +++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp @@ -1291,7 +1291,7 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily( break; case FAMILY_RV: m_settings.isArcticIsland = 1; - m_settings.isRaven = ASICREV_IS_RAVEN(uChipRevision); + m_settings.isRaven = ASICREV_IS_RAVEN(uChipRevision) || ASICREV_IS_RAVEN2(uChipRevision); if (m_settings.isRaven) { diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 2c70fb2c721..689f544c18b 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -314,6 +314,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, return false; } + /* Raven2 uses the same PCI IDs as Raven1, but different revision IDs. */ + if (info->family == CHIP_RAVEN && amdinfo->chip_rev >= 0x8) { + info->family = CHIP_RAVEN2; + info->name = "RAVEN2"; + } + if (info->family >= CHIP_VEGA10) info->chip_class = GFX9; else if (info->family >= CHIP_TONGA) diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c index cd3525187a0..69d9f7b9f3f 100644 --- a/src/amd/common/ac_llvm_util.c +++ b/src/amd/common/ac_llvm_util.c @@ -135,6 +135,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family) return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902"; case CHIP_VEGA20: return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902"; + case CHIP_RAVEN2: + return "gfx902"; /* TODO: use gfx909 when it's available */ default: return ""; } diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 94723dc9c09..1f7e2344625 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -151,6 +151,10 @@ static void addrlib_family_rev_id(enum radeon_family family, *addrlib_family = FAMILY_RV; *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE); break; + case CHIP_RAVEN2: + *addrlib_family = FAMILY_RV; + *addrlib_revid = get_first(AMDGPU_RAVEN2_RANGE); + break; default: fprintf(stderr, "amdgpu: Unknown family.\n"); } diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h index a282898be06..185ba029763 100644 --- a/src/amd/common/amd_family.h +++ b/src/amd/common/amd_family.h @@ -97,6 +97,7 @@ enum radeon_family { CHIP_VEGA12, CHIP_VEGA20, CHIP_RAVEN, + CHIP_RAVEN2, CHIP_LAST, }; diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h index d18e6655d33..2e790c54699 100644 --- a/src/amd/common/gfx9d.h +++ b/src/amd/common/gfx9d.h @@ -4457,6 +4457,9 @@ #define S_028424_OVERWRITE_COMBINER_WATERMARK(x) (((unsigned)(x) & 0x1F) << 2) #define G_028424_OVERWRITE_COMBINER_WATERMARK(x) (((x) >> 2) & 0x1F) #define C_028424_OVERWRITE_COMBINER_WATERMARK 0xFFFFFF83 +#define S_028424_DISABLE_CONSTANT_ENCODE_REG(x) (((unsigned)(x) & 0x1) << 10) /* Raven2+ */ +#define G_028424_DISABLE_CONSTANT_ENCODE_REG(x) (((x) >> 10) & 0x1) +#define C_028424_DISABLE_CONSTANT_ENCODE_REG 0xFFFFFBFF #define R_02842C_DB_STENCIL_CONTROL 0x02842C #define S_02842C_STENCILFAIL(x) (((unsigned)(x) & 0x0F) << 0) #define G_02842C_STENCILFAIL(x) (((x) >> 0) & 0x0F) |