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-rw-r--r--src/amd/vulkan/radv_image.c28
-rw-r--r--src/amd/vulkan/radv_meta_fast_clear.c25
-rw-r--r--src/amd/vulkan/radv_private.h1
3 files changed, 41 insertions, 13 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 8654e7f382c..ed520833981 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -454,7 +454,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
unsigned plane_id,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
- bool is_storage_image, uint32_t *state)
+ bool is_storage_image, bool disable_compression,
+ uint32_t *state)
{
struct radv_image_plane *plane = &image->planes[plane_id];
uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
@@ -479,7 +480,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (chip_class >= GFX8) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
- if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
+ if (!disable_compression && radv_dcc_enabled(image, first_level)) {
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
@@ -487,7 +488,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
meta_va |= dcc_tile_swizzle;
- } else if (!is_storage_image &&
+ } else if (!disable_compression &&
radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
}
@@ -1026,7 +1027,7 @@ radv_query_opaque_metadata(struct radv_device *device,
desc, NULL);
si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
- image->planes[0].surface.blk_w, false, false, desc);
+ image->planes[0].surface.blk_w, false, false, false, desc);
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
@@ -1400,8 +1401,8 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
struct radv_device *device,
VkFormat vk_format,
const VkComponentMapping *components,
- bool is_storage_image, unsigned plane_id,
- unsigned descriptor_plane_id)
+ bool is_storage_image, bool disable_compression,
+ unsigned plane_id, unsigned descriptor_plane_id)
{
struct radv_image *image = iview->image;
struct radv_image_plane *plane = &image->planes[plane_id];
@@ -1448,7 +1449,9 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
plane_id,
iview->base_mip,
iview->base_mip,
- blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
+ blk_w, is_stencil, is_storage_image,
+ is_storage_image || disable_compression,
+ descriptor->plane_descriptors[descriptor_plane_id]);
}
static unsigned
@@ -1589,10 +1592,17 @@ radv_image_view_init(struct radv_image_view *iview,
iview->base_mip = range->baseMipLevel;
iview->level_count = radv_get_levelCount(image, range);
+ bool disable_compression = extra_create_info ? extra_create_info->disable_compression: false;
for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
- radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
- radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
+ radv_image_view_make_descriptor(iview, device, format,
+ &pCreateInfo->components,
+ false, disable_compression,
+ iview->plane_id + i, i);
+ radv_image_view_make_descriptor(iview, device,
+ format, &pCreateInfo->components,
+ true, disable_compression,
+ iview->plane_id + i, i);
}
}
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index 6aaa85e5834..aa04f670556 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -782,7 +782,8 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
const VkImageSubresourceRange *subresourceRange)
{
struct radv_meta_saved_state saved_state;
- struct radv_image_view iview = {0};
+ struct radv_image_view load_iview = {0};
+ struct radv_image_view store_iview = {0};
struct radv_device *device = cmd_buffer->device;
/* This assumes the image is 2d with 1 layer */
@@ -819,7 +820,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
subresourceRange->baseMipLevel + l);
for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
- radv_image_view_init(&iview, cmd_buffer->device,
+ radv_image_view_init(&load_iview, cmd_buffer->device,
&(VkImageViewCreateInfo) {
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
@@ -833,6 +834,22 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
.layerCount = 1
},
}, NULL);
+ radv_image_view_init(&store_iview, cmd_buffer->device,
+ &(VkImageViewCreateInfo) {
+ .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
+ .image = radv_image_to_handle(image),
+ .viewType = VK_IMAGE_VIEW_TYPE_2D,
+ .format = image->vk_format,
+ .subresourceRange = {
+ .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
+ .baseMipLevel = subresourceRange->baseMipLevel + l,
+ .levelCount = 1,
+ .baseArrayLayer = subresourceRange->baseArrayLayer + s,
+ .layerCount = 1
+ },
+ }, &(struct radv_image_view_extra_create_info) {
+ .disable_compression = true
+ });
radv_meta_push_descriptor_set(cmd_buffer,
VK_PIPELINE_BIND_POINT_COMPUTE,
@@ -849,7 +866,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
.pImageInfo = (VkDescriptorImageInfo[]) {
{
.sampler = VK_NULL_HANDLE,
- .imageView = radv_image_view_to_handle(&iview),
+ .imageView = radv_image_view_to_handle(&load_iview),
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
},
}
@@ -863,7 +880,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
.pImageInfo = (VkDescriptorImageInfo[]) {
{
.sampler = VK_NULL_HANDLE,
- .imageView = radv_image_view_to_handle(&iview),
+ .imageView = radv_image_view_to_handle(&store_iview),
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
},
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index fbc4542cd72..1d87c17032c 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1883,6 +1883,7 @@ radv_image_from_gralloc(VkDevice device_h,
VkImage *out_image_h);
struct radv_image_view_extra_create_info {
+ bool disable_compression;
};
void radv_image_view_init(struct radv_image_view *view,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 13:48:53 +0000