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-rw-r--r--src/amd/common/ac_surface.c11
-rw-r--r--src/amd/common/ac_surface.h1
2 files changed, 8 insertions, 4 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 5cfd192118d..2c2917d4a23 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -488,7 +488,8 @@ static void ac_compute_cmask(const struct radeon_info *info,
unsigned num_pipes = info->num_tile_pipes;
unsigned cl_width, cl_height;
- if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
+ if (surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
+ (config->info.samples >= 2 && !surf->fmask_size))
return;
assert(info->chip_class <= GFX8);
@@ -850,7 +851,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
}
/* Compute FMASK. */
- if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
+ if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
+ !(surf->flags & RADEON_SURF_NO_FMASK)) {
ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
ADDR_TILEINFO fmask_tile_info = {};
@@ -1292,7 +1294,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
}
/* FMASK */
- if (in->numSamples > 1) {
+ if (in->numSamples > 1 && !(surf->flags & RADEON_SURF_NO_FMASK)) {
ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
@@ -1350,7 +1352,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
/* CMASK -- on GFX10 only for FMASK */
if (in->swizzleMode != ADDR_SW_LINEAR &&
- (info->chip_class <= GFX9 || in->numSamples > 1)) {
+ ((info->chip_class <= GFX9 && in->numSamples == 1) ||
+ (surf->fmask_size && in->numSamples >= 2))) {
ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index ca577b6e5db..53074c90faf 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -71,6 +71,7 @@ enum radeon_micro_mode {
#define RADEON_SURF_SHAREABLE (1 << 26)
#define RADEON_SURF_NO_RENDER_TARGET (1 << 27)
#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
+#define RADEON_SURF_NO_FMASK (1 << 29)
struct legacy_surf_level {
uint64_t offset;