diff options
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/common/ac_surface.c | 6 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index f8b9d2b70f8..9e45bd44b72 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -302,6 +302,12 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize; else surf_level->dcc_fast_clear_size = 0; + + /* Compute the DCC slice size because addrlib doesn't + * provide this info. As DCC memory is linear (each + * slice is the same size) it's easy to compute. + */ + surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size; } } diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 31623634936..8143c9f9a0e 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -212,6 +212,7 @@ struct radeon_surf { /* DCC and HTILE are very small. */ uint32_t dcc_size; + uint32_t dcc_slice_size; uint32_t dcc_alignment; uint32_t htile_size; |