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-rw-r--r--src/amd/common/ac_gpu_info.c3
-rw-r--r--src/amd/common/ac_gpu_info.h2
2 files changed, 0 insertions, 5 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 84a54bb094f..e55d864187d 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -301,9 +301,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
sizeof(amdinfo->gb_tile_mode));
info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
- memcpy(info->pa_sc_raster_config, amdinfo->pa_sc_raster_cfg,
- sizeof(info->pa_sc_raster_config));
- info->pa_sc_raster_config_1 = amdinfo->pa_sc_raster_cfg1[0];
memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
sizeof(amdinfo->gb_macro_tile_mode));
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 91d303aee40..06b0c775466 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -96,8 +96,6 @@ struct radeon_info {
uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
uint32_t pipe_interleave_bytes;
uint32_t enabled_rb_mask; /* GCN harvest config */
- uint32_t pa_sc_raster_config[4]; /* per SE */
- uint32_t pa_sc_raster_config_1;
uint64_t max_alignment; /* from addrlib */
/* Tile modes. */