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-rw-r--r--src/amd/addrlib/core/addrlib1.cpp16
-rw-r--r--src/amd/addrlib/core/addrlib1.h2
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.cpp8
-rw-r--r--src/amd/addrlib/r800/egbaddrlib.cpp34
-rw-r--r--src/amd/addrlib/r800/siaddrlib.cpp4
5 files changed, 32 insertions, 32 deletions
diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp
index 68959171658..922455bb5b9 100644
--- a/src/amd/addrlib/core/addrlib1.cpp
+++ b/src/amd/addrlib/core/addrlib1.cpp
@@ -180,7 +180,7 @@ ADDR_E_RETURNCODE AddrLib1::ComputeSurfaceInfo(
}
// Thick modes don't support multisample
- if (ComputeSurfaceThickness(pIn->tileMode) > 1 && pIn->numSamples > 1)
+ if (Thickness(pIn->tileMode) > 1 && pIn->numSamples > 1)
{
returnCode = ADDR_INVALIDPARAMS;
}
@@ -824,7 +824,7 @@ ADDR_E_RETURNCODE AddrLib1::ComputeFmaskInfo(
}
// No thick MSAA
- if (ComputeSurfaceThickness(pIn->tileMode) > 1)
+ if (Thickness(pIn->tileMode) > 1)
{
returnCode = ADDR_INVALIDPARAMS;
}
@@ -1203,7 +1203,7 @@ ADDR_E_RETURNCODE AddrLib1::GetTileIndex(
/**
***************************************************************************************************
-* AddrLib1::ComputeSurfaceThickness
+* AddrLib1::Thickness
*
* @brief
* Compute surface thickness
@@ -1212,7 +1212,7 @@ ADDR_E_RETURNCODE AddrLib1::GetTileIndex(
* Surface thickness
***************************************************************************************************
*/
-UINT_32 AddrLib1::ComputeSurfaceThickness(
+UINT_32 AddrLib1::Thickness(
AddrTileMode tileMode) ///< [in] tile mode
{
return m_modeFlags[tileMode].thickness;
@@ -2776,7 +2776,7 @@ UINT_32 AddrLib1::ComputePixelIndexWithinMicroTile(
UINT_32 z1 = _BIT(z, 1);
UINT_32 z2 = _BIT(z, 2);
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
// Compute the pixel number within the micro tile.
@@ -3007,7 +3007,7 @@ VOID AddrLib1::PadDimensions(
UINT_32 sliceAlign ///< [in] number of slice alignment
) const
{
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
ADDR_ASSERT(padDims <= 3);
@@ -3293,7 +3293,7 @@ BOOL_32 AddrLib1::OptimizeTileMode(
) const
{
AddrTileMode tileMode = pIn->tileMode;
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
// Optimization can only be done on level 0 and samples <= 1
if ((pIn->flags.opt4Space == TRUE) &&
@@ -3364,7 +3364,7 @@ AddrTileMode AddrLib1::DegradeLargeThickTile(
// Override tilemode
// When tile_width (8) * tile_height (8) * thickness * element_bytes is > row_size,
// it is better to just use THIN mode in this case
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
if (thickness > 1 && m_configFlags.allowLargeThickTile == 0)
{
diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h
index 94ca5a5b7cf..13d915a7fb5 100644
--- a/src/amd/addrlib/core/addrlib1.h
+++ b/src/amd/addrlib/core/addrlib1.h
@@ -425,7 +425,7 @@ protected:
//
static const AddrTileModeFlags m_modeFlags[ADDR_TM_COUNT];
- static UINT_32 ComputeSurfaceThickness(
+ static UINT_32 Thickness(
AddrTileMode tileMode);
// Checking tile mode
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index ccb05282647..7585e2558b0 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -636,7 +636,7 @@ ADDR_E_RETURNCODE CiAddrLib::HwlSetupTileCfg(
{
if (bpp > 0)
{
- UINT_32 thickness = ComputeSurfaceThickness(pCfgTable->mode);
+ UINT_32 thickness = Thickness(pCfgTable->mode);
UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
// Non-depth entries store a split factor
UINT_32 sampleSplit = m_tileTable[index].info.tileSplitBytes;
@@ -897,7 +897,7 @@ BOOL_32 CiAddrLib::HwlOverrideTileMode(
// UBTS#404321, we do not need such overriding, as THICK+THICK entries removed from the tile-mode table
if (!m_settings.isBonaire)
{
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
// tile_thickness = (array_mode == XTHICK) ? 8 : ((array_mode == THICK) ? 4 : 1)
if (thickness > 1)
@@ -1000,7 +1000,7 @@ VOID CiAddrLib::HwlSetupTileInfo(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
) const
{
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
ADDR_TILEINFO* pTileInfo = pTileInfoOut;
INT index = TileIndexInvalid;
INT macroModeIndex = TileIndexInvalid;
@@ -1546,7 +1546,7 @@ INT_32 CiAddrLib::HwlComputeMacroModeIndex(
AddrTileMode tileMode = m_tileTable[tileIndex].mode;
AddrTileType tileType = m_tileTable[tileIndex].type;
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
if (!IsMacroTiled(tileMode))
{
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 64c0c6225f5..52cf59b1b04 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -324,7 +324,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMicroTiled(
//
// Compute the micro tile thickness.
//
- microTileThickness = ComputeSurfaceThickness(expTileMode);
+ microTileThickness = Thickness(expTileMode);
//
// Extra override for mip levels
@@ -455,7 +455,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(
//
// Compute the micro tile thickness.
//
- microTileThickness = ComputeSurfaceThickness(expTileMode);
+ microTileThickness = Thickness(expTileMode);
//
// Find the correct tiling mode for mip levels
@@ -481,7 +481,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(
}
else
{
- if (microTileThickness != ComputeSurfaceThickness(expTileMode))
+ if (microTileThickness != Thickness(expTileMode))
{
//
// Re-compute if thickness changed since bank-height may be changed!
@@ -811,7 +811,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMacroTiled(
UINT_32 bankHeightAlign;
UINT_32 macroAspectAlign;
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
UINT_32 pipes = HwlGetPipes(pTileInfo);
//
@@ -1027,7 +1027,7 @@ AddrTileMode EgBasedAddrLib::ComputeSurfaceMipLevelTileMode(
UINT_32 bytesPerTile;
AddrTileMode expTileMode = baseTileMode;
- UINT_32 microTileThickness = ComputeSurfaceThickness(expTileMode);
+ UINT_32 microTileThickness = Thickness(expTileMode);
UINT_32 interleaveSize = m_pipeInterleaveBytes * m_bankInterleave;
//
@@ -1190,7 +1190,7 @@ AddrTileMode EgBasedAddrLib::HwlDegradeThickTileMode(
UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per slice
) const
{
- ADDR_ASSERT(numSlices < ComputeSurfaceThickness(baseTileMode));
+ ADDR_ASSERT(numSlices < Thickness(baseTileMode));
// if pBytesPerTile is NULL, this is a don't-care....
UINT_32 bytesPerTile = pBytesPerTile != NULL ? *pBytesPerTile : 64;
@@ -1306,7 +1306,7 @@ UINT_64 EgBasedAddrLib::DispatchComputeSurfaceAddrFromCoord(
/// mipmap chain must have the same tileType, so please fill tileType correctly
if (IsLinear(pIn->tileMode) == FALSE)
{
- if (bpp >= 128 || ComputeSurfaceThickness(tileMode) > 1)
+ if (bpp >= 128 || Thickness(tileMode) > 1)
{
ADDR_ASSERT(microTileType != ADDR_DISPLAYABLE);
}
@@ -1474,7 +1474,7 @@ UINT_64 EgBasedAddrLib::ComputeSurfaceAddrFromCoordMacroTiled(
UINT_32 tileIndex;
UINT_32 tileOffset;
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
//
// Compute the number of group, pipe, and bank bits.
@@ -1726,7 +1726,7 @@ UINT_64 EgBasedAddrLib::ComputeSurfaceAddrFromCoordMicroTiled(
UINT_32 pixelIndex;
UINT_32 pixelOffset;
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
//
// Compute the micro tile size.
@@ -1839,7 +1839,7 @@ VOID EgBasedAddrLib::HwlComputePixelCoordFromOffset(
UINT_32 x = 0;
UINT_32 y = 0;
UINT_32 z = 0;
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
// For planar surface, we adjust offset acoording to tile base
if ((bpp != compBits) && (compBits != 0) && isDepthSampleOrder)
@@ -2053,7 +2053,7 @@ VOID EgBasedAddrLib::DispatchComputeSurfaceCoordFromAddr(
/// mipmap chain must have the same tileType, so please fill tileType correctly
if (IsLinear(pIn->tileMode) == FALSE)
{
- if (bpp >= 128 || ComputeSurfaceThickness(tileMode) > 1)
+ if (bpp >= 128 || Thickness(tileMode) > 1)
{
ADDR_ASSERT(microTileType != ADDR_DISPLAYABLE);
}
@@ -2207,7 +2207,7 @@ VOID EgBasedAddrLib::ComputeSurfaceCoordFromAddrMacroTiled(
(((addrBits / groupBits / pipes) % bankInterleave) * groupBits) +
(((addrBits / groupBits / pipes) / bankInterleave) / banks) * groupBits * bankInterleave;
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
UINT_32 microTileBits = bpp * microTileThickness * MicroTilePixels * numSamples;
@@ -2365,7 +2365,7 @@ VOID EgBasedAddrLib::ComputeSurfaceCoord2DFromBankPipe(
break;
}
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
bank ^= tileSplitRotation * tileSlices;
if (pipeRotation == 0)
@@ -2703,7 +2703,7 @@ UINT_32 EgBasedAddrLib::ComputeSliceTileSwizzle(
if (IsMacroTiled(tileMode)) // Swizzle only for macro tile mode
{
- UINT_32 firstSlice = slice / ComputeSurfaceThickness(tileMode);
+ UINT_32 firstSlice = slice / Thickness(tileMode);
UINT_32 numPipes = HwlGetPipes(pTileInfo);
UINT_32 numBanks = pTileInfo->banks;
@@ -2859,7 +2859,7 @@ UINT_32 EgBasedAddrLib::ComputeBankFromCoord(
//
// Compute bank rotation for the slice.
//
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
switch (tileMode)
{
@@ -3281,7 +3281,7 @@ UINT_64 EgBasedAddrLib::DispatchComputeFmaskAddrFromCoord(
UINT_64 addr = 0;
ADDR_ASSERT(numSamples > 1);
- ADDR_ASSERT(ComputeSurfaceThickness(tileMode) == 1);
+ ADDR_ASSERT(Thickness(tileMode) == 1);
switch (tileMode)
{
@@ -4512,7 +4512,7 @@ UINT_32 EgBasedAddrLib::HwlGetPitchAlignmentMicroTiled(
{
UINT_32 pitchAlign;
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
UINT_32 pixelsPerMicroTile;
UINT_32 pixelsPerPipeInterleave;
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index 5d725e66e1f..694c0f3a4bb 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -292,7 +292,7 @@ UINT_32 SiAddrLib::ComputePipeFromCoord(
}
pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3);
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
//
// Apply pipe rotation for the slice.
@@ -1460,7 +1460,7 @@ VOID SiAddrLib::HwlSetupTileInfo(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
) const
{
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
ADDR_TILEINFO* pTileInfo = pTileInfoOut;
INT index = TileIndexInvalid;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 05:00:13 +0000