diff options
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/common/ac_llvm_util.c | 1 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.c | 33 | ||||
| -rw-r--r-- | src/amd/common/amd_family.h | 1 |
3 files changed, 28 insertions, 7 deletions
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c index bb9e873af81..f3db1c5a4a4 100644 --- a/src/amd/common/ac_llvm_util.c +++ b/src/amd/common/ac_llvm_util.c @@ -114,6 +114,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family) case CHIP_POLARIS12: return "polaris11"; case CHIP_VEGA10: + case CHIP_VEGA12: case CHIP_RAVEN: return "gfx900"; default: diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 603b7058bdc..12dfc0cb1f2 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -135,6 +135,10 @@ static void addrlib_family_rev_id(enum radeon_family family, *addrlib_family = FAMILY_AI; *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE); break; + case CHIP_VEGA12: + *addrlib_family = FAMILY_AI; + *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE); + break; case CHIP_RAVEN: *addrlib_family = FAMILY_RV; *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE); @@ -905,8 +909,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT); hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT); - hin.hTileFlags.pipeAligned = 1; - hin.hTileFlags.rbAligned = 1; + hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned; + hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned; hin.depthFlags = in->flags; hin.swizzleMode = in->swizzleMode; hin.unalignedWidth = in->width; @@ -967,8 +971,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT); dout.pMipInfo = meta_mip_info; - din.dccKeyFlags.pipeAligned = 1; - din.dccKeyFlags.rbAligned = 1; + din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned; + din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned; din.colorFlags = in->flags; din.resourceType = in->resourceType; din.swizzleMode = in->swizzleMode; @@ -1088,8 +1092,14 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT); cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT); - cin.cMaskFlags.pipeAligned = 1; - cin.cMaskFlags.rbAligned = 1; + if (in->numSamples) { + /* FMASK is always aligned. */ + cin.cMaskFlags.pipeAligned = 1; + cin.cMaskFlags.rbAligned = 1; + } else { + cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned; + cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned; + } cin.colorFlags = in->flags; cin.resourceType = in->resourceType; cin.unalignedWidth = in->width; @@ -1116,6 +1126,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, } static int gfx9_compute_surface(ADDR_HANDLE addrlib, + const struct radeon_info *info, const struct ac_surf_config *config, enum radeon_surf_mode mode, struct radeon_surf *surf) @@ -1196,6 +1207,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, else AddrSurfInfoIn.numSlices = config->info.array_size; + /* This is propagated to HTILE/DCC/CMASK. */ + AddrSurfInfoIn.flags.metaPipeUnaligned = 0; + AddrSurfInfoIn.flags.metaRbUnaligned = 0; + switch (mode) { case RADEON_SURF_MODE_LINEAR_ALIGNED: assert(config->info.samples <= 1); @@ -1321,6 +1336,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, assert(0); } + /* Temporary workaround to prevent VM faults and hangs. */ + if (info->family == CHIP_VEGA12) + surf->u.gfx9.fmask_size *= 8; + return 0; } @@ -1336,7 +1355,7 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, return r; if (info->chip_class >= GFX9) - return gfx9_compute_surface(addrlib, config, mode, surf); + return gfx9_compute_surface(addrlib, info, config, mode, surf); else return gfx6_compute_surface(addrlib, info, config, mode, surf); } diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h index c62d0aa527a..285111f2a2a 100644 --- a/src/amd/common/amd_family.h +++ b/src/amd/common/amd_family.h @@ -93,6 +93,7 @@ enum radeon_family { CHIP_POLARIS11, CHIP_POLARIS12, CHIP_VEGA10, + CHIP_VEGA12, CHIP_RAVEN, CHIP_LAST, }; |