diff options
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_meta_blit2d.c | 9 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_meta_buffer.c | 4 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_query.c | 6 |
3 files changed, 7 insertions, 12 deletions
diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c index 85e2d4678e9..cac0a4dd55f 100644 --- a/src/amd/vulkan/radv_meta_blit2d.c +++ b/src/amd/vulkan/radv_meta_blit2d.c @@ -608,8 +608,7 @@ build_nir_copy_fragment_shader(struct radv_device *device, } nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in)); - unsigned swiz[4] = { 0, 1 }; - nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false); + nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3); nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled); nir_store_var(&b, color_out, color, 0xf); @@ -642,8 +641,7 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device, } nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in)); - unsigned swiz[4] = { 0, 1 }; - nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false); + nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3); nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled); nir_store_var(&b, color_out, color, 0x1); @@ -676,8 +674,7 @@ build_nir_copy_fragment_shader_stencil(struct radv_device *device, } nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in)); - unsigned swiz[4] = { 0, 1 }; - nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false); + nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3); nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled); nir_store_var(&b, color_out, color, 0x1); diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index c8558216bf1..6c6d1cc41d7 100644 --- a/src/amd/vulkan/radv_meta_buffer.c +++ b/src/amd/vulkan/radv_meta_buffer.c @@ -25,7 +25,7 @@ build_buffer_fill_shader(struct radv_device *dev) nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id); nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16)); - offset = nir_swizzle(&b, offset, (unsigned[]) {0, 0, 0, 0}, 1, false); + offset = nir_channel(&b, offset, 0); nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader, nir_intrinsic_vulkan_resource_index); @@ -77,7 +77,7 @@ build_buffer_copy_shader(struct radv_device *dev) nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id); nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16)); - offset = nir_swizzle(&b, offset, (unsigned[]) {0, 0, 0, 0}, 1, false); + offset = nir_channel(&b, offset, 0); nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader, nir_intrinsic_vulkan_resource_index); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 16c39aa135d..e3229ab59bb 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -188,10 +188,8 @@ build_occlusion_query_shader(struct radv_device *device) { load->num_components = 2; nir_builder_instr_insert(&b, &load->instr); - const unsigned swizzle0[] = {0,0,0,0}; - const unsigned swizzle1[] = {1,1,1,1}; - nir_store_var(&b, start, nir_swizzle(&b, &load->dest.ssa, swizzle0, 1, false), 0x1); - nir_store_var(&b, end, nir_swizzle(&b, &load->dest.ssa, swizzle1, 1, false), 0x1); + nir_store_var(&b, start, nir_channel(&b, &load->dest.ssa, 0), 0x1); + nir_store_var(&b, end, nir_channel(&b, &load->dest.ssa, 1), 0x1); nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0)); nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0)); |