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-rw-r--r--src/amd/addrlib/core/addrcommon.h2
-rw-r--r--src/amd/addrlib/core/addrelemlib.cpp22
-rw-r--r--src/amd/addrlib/core/addrelemlib.h2
-rw-r--r--src/amd/addrlib/core/addrlib.cpp2
-rw-r--r--src/amd/addrlib/core/addrlib.h31
-rw-r--r--src/amd/addrlib/core/addrlib1.cpp17
-rw-r--r--src/amd/addrlib/core/addrlib1.h2
-rw-r--r--src/amd/addrlib/core/addrobject.cpp2
-rw-r--r--src/amd/addrlib/core/addrobject.h2
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.cpp14
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.h2
-rw-r--r--src/amd/addrlib/r800/egbaddrlib.cpp15
-rw-r--r--src/amd/addrlib/r800/siaddrlib.cpp28
13 files changed, 68 insertions, 73 deletions
diff --git a/src/amd/addrlib/core/addrcommon.h b/src/amd/addrlib/core/addrcommon.h
index 9b0cc6dafa9..caed63f8498 100644
--- a/src/amd/addrlib/core/addrcommon.h
+++ b/src/amd/addrlib/core/addrcommon.h
@@ -27,7 +27,7 @@
/**
****************************************************************************************************
* @file addrcommon.h
-* @brief Contains the helper function and constants
+* @brief Contains the helper function and constants.
****************************************************************************************************
*/
diff --git a/src/amd/addrlib/core/addrelemlib.cpp b/src/amd/addrlib/core/addrelemlib.cpp
index b894f49cca6..c9d20742ee1 100644
--- a/src/amd/addrlib/core/addrelemlib.cpp
+++ b/src/amd/addrlib/core/addrelemlib.cpp
@@ -27,7 +27,7 @@
/**
****************************************************************************************************
* @file addrelemlib.cpp
-* @brief Contains the class implementation for element/pixel related functions
+* @brief Contains the class implementation for element/pixel related functions.
****************************************************************************************************
*/
@@ -720,7 +720,7 @@ VOID ElemLib::GetCompType(
*/
VOID ElemLib::GetCompSwap(
AddrSurfaceSwap swap, ///< [in] swap mode
- PixelFormatInfo* pInfo) ///< [in/out] output per component info
+ PixelFormatInfo* pInfo) ///< [in,out] output per component info
{
switch (pInfo->comps)
{
@@ -811,7 +811,7 @@ VOID ElemLib::GetCompSwap(
VOID ElemLib::SwapComps(
UINT_32 c0, ///< [in] component index 0
UINT_32 c1, ///< [in] component index 1
- PixelFormatInfo* pInfo) ///< [in/out] output per component info
+ PixelFormatInfo* pInfo) ///< [in,out] output per component info
{
UINT_32 start;
UINT_32 bits;
@@ -1127,10 +1127,10 @@ VOID ElemLib::AdjustSurfaceInfo(
ElemMode elemMode, ///< [in] element mode
UINT_32 expandX, ///< [in] decompression expansion factor in X
UINT_32 expandY, ///< [in] decompression expansion factor in Y
- UINT_32* pBpp, ///< [in/out] bpp
- UINT_32* pBasePitch, ///< [in/out] base pitch
- UINT_32* pWidth, ///< [in/out] width
- UINT_32* pHeight) ///< [in/out] height
+ UINT_32* pBpp, ///< [in,out] bpp
+ UINT_32* pBasePitch, ///< [in,out] base pitch
+ UINT_32* pWidth, ///< [in,out] width
+ UINT_32* pHeight) ///< [in,out] height
{
UINT_32 packedBits;
UINT_32 basePitch;
@@ -1252,9 +1252,9 @@ VOID ElemLib::RestoreSurfaceInfo(
ElemMode elemMode, ///< [in] element mode
UINT_32 expandX, ///< [in] decompression expansion factor in X
UINT_32 expandY, ///< [out] decompression expansion factor in Y
- UINT_32* pBpp, ///< [in/out] bpp
- UINT_32* pWidth, ///< [in/out] width
- UINT_32* pHeight) ///< [in/out] height
+ UINT_32* pBpp, ///< [in,out] bpp
+ UINT_32* pWidth, ///< [in,out] width
+ UINT_32* pHeight) ///< [in,out] height
{
UINT_32 originalBits;
UINT_32 width;
@@ -1561,7 +1561,7 @@ VOID ElemLib::GetCompBits(
****************************************************************************************************
*/
VOID ElemLib::SetClearComps(
- ADDR_FLT_32 comps[4], ///< [in/out] components
+ ADDR_FLT_32 comps[4], ///< [in,out] components
BOOL_32 clearColor, ///< [in] TRUE if clear color is set (CLEAR_COLOR)
BOOL_32 float32) ///< [in] TRUE if float32 component (BLEND_FLOAT32)
{
diff --git a/src/amd/addrlib/core/addrelemlib.h b/src/amd/addrlib/core/addrelemlib.h
index 2875026e32e..c95c9d63839 100644
--- a/src/amd/addrlib/core/addrelemlib.h
+++ b/src/amd/addrlib/core/addrelemlib.h
@@ -27,7 +27,7 @@
/**
****************************************************************************************************
* @file addrelemlib.h
-* @brief Contains the class for element/pixel related functions
+* @brief Contains the class for element/pixel related functions.
****************************************************************************************************
*/
diff --git a/src/amd/addrlib/core/addrlib.cpp b/src/amd/addrlib/core/addrlib.cpp
index 8553ca6569f..d4b31e61e5a 100644
--- a/src/amd/addrlib/core/addrlib.cpp
+++ b/src/amd/addrlib/core/addrlib.cpp
@@ -27,7 +27,7 @@
/**
****************************************************************************************************
* @file addrlib.cpp
-* @brief Contains the implementation for the AddrLib base class..
+* @brief Contains the implementation for the Addr::Lib class.
****************************************************************************************************
*/
diff --git a/src/amd/addrlib/core/addrlib.h b/src/amd/addrlib/core/addrlib.h
index 10d029f34fe..e5d4c57e857 100644
--- a/src/amd/addrlib/core/addrlib.h
+++ b/src/amd/addrlib/core/addrlib.h
@@ -27,7 +27,7 @@
/**
****************************************************************************************************
* @file addrlib.h
-* @brief Contains the AddrLib base class definition.
+* @brief Contains the Addr::Lib base class definition.
****************************************************************************************************
*/
@@ -56,10 +56,6 @@
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
-#ifndef CIASICIDGFXENGINE_SEAISLAND
-#define CIASICIDGFXENGINE_SEAISLAND 0x0000000B
-#endif
-
namespace Addr
{
@@ -227,36 +223,36 @@ private:
VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
protected:
- LibClass m_class; ///< Store class type (HWL type)
+ LibClass m_class; ///< Store class type (HWL type)
- ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h
+ ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h
- UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
+ UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
- UINT_32 m_version; ///< Current version
+ UINT_32 m_version; ///< Current version
//
// Global parameters
//
- ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by
+ ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by
/// AddrLib instead of Client except forceLinearAligned
- UINT_32 m_pipes; ///< Number of pipes
- UINT_32 m_banks; ///< Number of banks
+ UINT_32 m_pipes; ///< Number of pipes
+ UINT_32 m_banks; ///< Number of banks
/// For r800 this is MC_ARB_RAMCFG.NOOFBANK
/// Keep it here to do default parameter calculation
- UINT_32 m_pipeInterleaveBytes;
+ UINT_32 m_pipeInterleaveBytes;
///< Specifies the size of contiguous address space
/// within each tiling pipe when making linear
/// accesses. (Formerly Group Size)
- UINT_32 m_rowSize; ///< DRAM row size, in bytes
+ UINT_32 m_rowSize; ///< DRAM row size, in bytes
- UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
- UINT_32 m_maxSamples; ///< Max numSamples
+ UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
+ UINT_32 m_maxSamples; ///< Max numSamples
private:
- ElemLib* m_pElemLib; ///< Element Lib pointer
+ ElemLib* m_pElemLib; ///< Element Lib pointer
};
Lib* SiHwlInit (const Client* pClient);
@@ -265,4 +261,3 @@ Lib* CiHwlInit (const Client* pClient);
} // Addr
#endif
-
diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp
index e7ac3859a81..f0cd58ca41b 100644
--- a/src/amd/addrlib/core/addrlib1.cpp
+++ b/src/amd/addrlib/core/addrlib1.cpp
@@ -27,7 +27,7 @@
/**
****************************************************************************************************
* @file addr1lib.cpp
-* @brief Contains the implementation for the AddrLib1 base class..
+* @brief Contains the implementation for the Addr::V1::Lib base class.
****************************************************************************************************
*/
@@ -1706,7 +1706,6 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskCoordFromAddr(
return returnCode;
}
-
/**
****************************************************************************************************
* Lib::ComputeTileDataWidthAndHeight
@@ -3225,14 +3224,14 @@ VOID Lib::PadDimensions(
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure.
+ ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
- UINT_32* pPitch, ///< [in/out] pitch in pixels
+ UINT_32* pPitch, ///< [in,out] pitch in pixels
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pHeight, ///< [in/out] height in pixels
+ UINT_32* pHeight, ///< [in,out] height in pixels
UINT_32 heightAlign, ///< [in] height alignment
- UINT_32* pSlices, ///< [in/out] number of slices
+ UINT_32* pSlices, ///< [in,out] number of slices
UINT_32 sliceAlign ///< [in] number of slice alignment
) const
{
@@ -3487,7 +3486,7 @@ BOOL_32 Lib::IsPrtTileMode(
****************************************************************************************************
*/
VOID Lib::ComputeMipLevel(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in/out] Input structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
) const
{
if (ElemLib::IsBlockCompressed(pIn->format))
@@ -3656,7 +3655,7 @@ AddrTileMode Lib::DegradeLargeThickTile(
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::PostComputeMipLevel(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in/out] Input structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in,out] Input structure
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output structure
) const
{
@@ -3737,7 +3736,7 @@ UINT_32 Lib::HwlGetPipes(
****************************************************************************************************
*/
BOOL_32 Lib::ComputeQbStereoInfo(
- ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in/out] updated pOut+pStereoInfo
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] updated pOut+pStereoInfo
) const
{
BOOL_32 success = FALSE;
diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h
index 7c19d102c16..9c66f53e737 100644
--- a/src/amd/addrlib/core/addrlib1.h
+++ b/src/amd/addrlib/core/addrlib1.h
@@ -27,7 +27,7 @@
/**
****************************************************************************************************
* @file addrlib1.h
-* @brief Contains the Lib base class definition.
+* @brief Contains the Addr::V1::Lib class definition.
****************************************************************************************************
*/
diff --git a/src/amd/addrlib/core/addrobject.cpp b/src/amd/addrlib/core/addrobject.cpp
index 0c5f81a5185..cb62aa0fdec 100644
--- a/src/amd/addrlib/core/addrobject.cpp
+++ b/src/amd/addrlib/core/addrobject.cpp
@@ -26,7 +26,7 @@
/**
****************************************************************************************************
-* @file Object.cpp
+* @file addrobject.cpp
* @brief Contains the Object base class implementation.
****************************************************************************************************
*/
diff --git a/src/amd/addrlib/core/addrobject.h b/src/amd/addrlib/core/addrobject.h
index c6483862b56..031103b7374 100644
--- a/src/amd/addrlib/core/addrobject.h
+++ b/src/amd/addrlib/core/addrobject.h
@@ -26,7 +26,7 @@
/**
****************************************************************************************************
-* @file Object.h
+* @file addrobject.h
* @brief Contains the Object base class definition.
****************************************************************************************************
*/
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 839a26833a6..3c0607ef266 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -861,7 +861,7 @@ VOID CiLib::HwlFmaskPostThunkSurfInfo(
AddrTileMode CiLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
- UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per slice
+ UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per slice
) const
{
return baseTileMode;
@@ -880,7 +880,7 @@ AddrTileMode CiLib::HwlDegradeThickTileMode(
****************************************************************************************************
*/
VOID CiLib::HwlOverrideTileMode(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in/out] input output structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
) const
{
AddrTileMode tileMode = pInOut->tileMode;
@@ -1041,7 +1041,7 @@ VOID CiLib::HwlOverrideTileMode(
****************************************************************************************************
*/
VOID CiLib::HwlSelectTileMode(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in/out] input output structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
) const
{
AddrTileMode tileMode;
@@ -1956,14 +1956,14 @@ VOID CiLib::HwlPadDimensions(
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure.
+ ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
- UINT_32* pPitch, ///< [in/out] pitch in pixels
+ UINT_32* pPitch, ///< [in,out] pitch in pixels
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pHeight, ///< [in/out] height in pixels
+ UINT_32* pHeight, ///< [in,out] height in pixels
UINT_32 heightAlign, ///< [in] height alignment
- UINT_32* pSlices, ///< [in/out] number of slices
+ UINT_32* pSlices, ///< [in,out] number of slices
UINT_32 sliceAlign ///< [in] number of slice alignment
) const
{
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 438790a5895..a9b1607ff1d 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -57,7 +57,7 @@ struct CIChipSettings
UINT_32 isSpectre : 1;
UINT_32 isSpooky : 1;
UINT_32 isKalindi : 1;
- // Hawaii is GFXIP 7.2, similar with CI (Bonaire)
+ // Hawaii is GFXIP 7.2
UINT_32 isHawaii : 1;
// VI
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 5de3f996f08..b15168263f3 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -27,7 +27,7 @@
/**
****************************************************************************************************
* @file egbaddrlib.cpp
-* @brief Contains the EgBasedLib class implementation
+* @brief Contains the EgBasedLib class implementation.
****************************************************************************************************
*/
@@ -49,7 +49,8 @@ namespace V1
*
****************************************************************************************************
*/
-EgBasedLib::EgBasedLib(const Client* pClient) :
+EgBasedLib::EgBasedLib(const Client* pClient)
+ :
Lib(pClient),
m_ranks(0),
m_logicalBanks(0),
@@ -743,7 +744,7 @@ BOOL_32 EgBasedLib::HwlReduceBankWidthHeight(
UINT_32 numSamples, ///< [in] number of samples
UINT_32 bankHeightAlign, ///< [in] bank height alignment
UINT_32 pipes, ///< [in] pipes
- ADDR_TILEINFO* pTileInfo ///< [in/out] bank structure.
+ ADDR_TILEINFO* pTileInfo ///< [in,out] bank structure.
) const
{
UINT_32 macroAspectAlign;
@@ -846,7 +847,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 mipLevel, ///< [in] mip level
UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure.
+ ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32* pBaseAlign, ///< [out] base address alignment in bytes
UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels
UINT_32* pHeightAlign, ///< [out] height alignment in pixels
@@ -1247,7 +1248,7 @@ BOOL_32 EgBasedLib::HwlDegradeBaseLevel(
AddrTileMode EgBasedLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
- UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per slice
+ UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per slice
) const
{
ADDR_ASSERT(numSlices < Thickness(baseTileMode));
@@ -4755,8 +4756,8 @@ UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled(
UINT_32 numSamples, ///< [in] number of samples
UINT_32 baseAlign, ///< [in] base alignment
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pPitch, ///< [in/out] pointer to pitch
- UINT_32* pHeight ///< [in/out] pointer to height
+ UINT_32* pPitch, ///< [in,out] pointer to pitch
+ UINT_32* pHeight ///< [in,out] pointer to height
) const
{
UINT_64 logicalSliceSize;
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index 9d3f5aa9367..f1f5a1bb9ec 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -1527,9 +1527,9 @@ UINT_64 SiLib::HwlGetSizeAdjustmentLinear(
UINT_32 numSamples, ///< [in] number of samples
UINT_32 baseAlign, ///< [in] base alignment
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pPitch, ///< [in/out] pointer to pitch
- UINT_32* pHeight, ///< [in/out] pointer to height
- UINT_32* pHeightAlign ///< [in/out] pointer to height align
+ UINT_32* pPitch, ///< [in,out] pointer to pitch
+ UINT_32* pHeight, ///< [in,out] pointer to height
+ UINT_32* pHeightAlign ///< [in,out] pointer to height align
) const
{
UINT_64 sliceSize;
@@ -1682,8 +1682,8 @@ UINT_64 SiLib::HwlGetSizeAdjustmentMicroTiled(
UINT_32 numSamples, ///< [in] number of samples
UINT_32 baseAlign, ///< [in] base alignment
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pPitch, ///< [in/out] pointer to pitch
- UINT_32* pHeight ///< [in/out] pointer to height
+ UINT_32* pPitch, ///< [in,out] pointer to pitch
+ UINT_32* pHeight ///< [in,out] pointer to height
) const
{
UINT_64 logicalSliceSize;
@@ -2316,8 +2316,8 @@ UINT_32 SiLib::HwlComputeXmaskCoordYFrom8Pipe(
*/
VOID SiLib::HwlComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, ///< [in] tile mode
- UINT_32* pX, ///< [in/out] x coordinate
- UINT_32* pY, ///< [in/out] y coordinate
+ UINT_32* pX, ///< [in,out] x coordinate
+ UINT_32* pY, ///< [in,out] y coordinate
UINT_32 slice, ///< [in] slice index
UINT_32 bank, ///< [in] bank number
UINT_32 pipe, ///< [in] pipe number
@@ -2555,7 +2555,7 @@ ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
****************************************************************************************************
*/
BOOL_32 SiLib::HwlComputeMipLevel(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in/out] Input structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
) const
{
// basePitch is calculated from level 0 so we only check this for mipLevel > 0
@@ -2595,7 +2595,7 @@ BOOL_32 SiLib::HwlComputeMipLevel(
*/
VOID SiLib::HwlCheckLastMacroTiledLvl(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure
- ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in/out] Output structure (used as input, too)
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] Output structure (used as input, too)
) const
{
// pow2Pad covers all mipmap cases
@@ -2672,7 +2672,7 @@ VOID SiLib::HwlCheckLastMacroTiledLvl(
AddrTileMode SiLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
- UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per slice
+ UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per slice
) const
{
return EgBasedLib::HwlDegradeThickTileMode(baseTileMode, numSlices, pBytesPerTile);
@@ -3146,7 +3146,7 @@ UINT_32 SiLib::HwlComputeFmaskBits(
****************************************************************************************************
*/
VOID SiLib::HwlOverrideTileMode(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in/out] input output structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
) const
{
AddrTileMode tileMode = pInOut->tileMode;
@@ -3216,7 +3216,7 @@ VOID SiLib::HwlOverrideTileMode(
****************************************************************************************************
*/
VOID SiLib::HwlSelectTileMode(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in/out] input output structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
) const
{
AddrTileMode tileMode;
@@ -3508,9 +3508,9 @@ VOID SiLib::InitEquationTable()
****************************************************************************************************
*/
BOOL_32 SiLib::IsEquationSupported(
- UINT_32 bpp, ///< Bits per pixel
+ UINT_32 bpp, ///< Bits per pixel
TileConfig tileConfig, ///< Tile config
- INT_32 tileIndex ///< Tile index
+ INT_32 tileIndex ///< Tile index
) const
{
BOOL_32 supported = TRUE;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 01:51:31 +0000