diff options
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 10 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 9 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 2 |
6 files changed, 13 insertions, 13 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 3f3a236ba80..49ad93407ec 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -457,6 +457,16 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9; + /* Some chips have RB+ registers, but don't support RB+. Those must + * always disable it. + */ + info->rbplus_allowed = info->has_rbplus && + (info->family == CHIP_STONEY || + info->family == CHIP_VEGA12 || + info->family == CHIP_RAVEN || + info->family == CHIP_RAVEN2 || + info->family == CHIP_RENOIR); + info->has_out_of_order_rast = info->chip_class >= GFX8 && info->max_se >= 2; diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 0f802216bdc..f676600e5b9 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -62,6 +62,7 @@ struct radeon_info { bool has_distributed_tess; bool has_dcc_constant_encode; bool has_rbplus; /* if RB+ registers exist */ + bool rbplus_allowed; /* if RB+ is allowed */ bool has_load_ctx_reg_pkt; bool has_out_of_order_rast; bool cpdma_prefetch_writes_memory; diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7031428a996..aed2e9f8909 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -988,7 +988,7 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, static void radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer) { - if (!cmd_buffer->device->physical_device->rbplus_allowed) + if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed) return; struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index ce487aa2eda..265a7bd7912 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -354,15 +354,6 @@ radv_physical_device_init(struct radv_physical_device *device, radv_get_driver_uuid(&device->driver_uuid); radv_get_device_uuid(&device->rad_info, &device->device_uuid); - if (device->rad_info.family == CHIP_STONEY || - device->rad_info.chip_class >= GFX9) { - device->rbplus_allowed = device->rad_info.family == CHIP_STONEY || - device->rad_info.family == CHIP_VEGA12 || - device->rad_info.family == CHIP_RAVEN || - device->rad_info.family == CHIP_RAVEN2 || - device->rad_info.family == CHIP_RENOIR; - } - device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast && !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 0a5d94fd5f3..ecd4edf6500 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4055,7 +4055,7 @@ radv_compute_db_shader_control(const struct radv_device *device, z_order = V_02880C_LATE_Z; bool disable_rbplus = device->physical_device->rad_info.has_rbplus && - !device->physical_device->rbplus_allowed; + !device->physical_device->rad_info.rbplus_allowed; /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled * but this appears to break Project Cars (DXVK). See diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index b3d6d56e4ac..219495ef3d6 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -280,8 +280,6 @@ struct radv_physical_device { int master_fd; struct wsi_device wsi_device; - bool rbplus_allowed; /* if RB+ is allowed */ - bool out_of_order_rast_allowed; /* Whether DCC should be enabled for MSAA textures. */ |