diff options
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 8 | ||||
-rw-r--r-- | src/amd/vulkan/radv_image.c | 1 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta.h | 3 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 36 | ||||
-rw-r--r-- | src/amd/vulkan/radv_private.h | 1 |
5 files changed, 32 insertions, 17 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index ef659a6c48c..e35ccf80956 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4892,14 +4892,16 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe } static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, uint32_t value) + struct radv_image *image, + const VkImageSubresourceRange *range, + uint32_t value) { struct radv_cmd_state *state = &cmd_buffer->state; state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; - state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value); + state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value); state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; } @@ -5005,7 +5007,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, value = 0xccccccccu; } - radv_initialise_cmask(cmd_buffer, image, value); + radv_initialise_cmask(cmd_buffer, image, range, value); } if (radv_image_has_fmask(image)) { diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index ca007d1dd65..4099c57aa85 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -942,6 +942,7 @@ radv_image_get_cmask_info(struct radv_device *device, out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max; out->alignment = image->planes[0].surface.cmask_alignment; + out->slice_size = image->planes[0].surface.cmask_slice_size; out->size = image->planes[0].surface.cmask_size; } diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h index 30981f00790..c3d37bb07d2 100644 --- a/src/amd/vulkan/radv_meta.h +++ b/src/amd/vulkan/radv_meta.h @@ -212,7 +212,8 @@ void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer, const VkImageResolve *regions); uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, uint32_t value); + struct radv_image *image, + const VkImageSubresourceRange *range, uint32_t value); uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value); diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 0a9d9e76ca4..4d569729dda 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1326,11 +1326,21 @@ radv_get_cmask_fast_clear_value(const struct radv_image *image) uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, uint32_t value) + struct radv_image *image, + const VkImageSubresourceRange *range, uint32_t value) { - return radv_fill_buffer(cmd_buffer, image->bo, - image->offset + image->cmask.offset, - image->cmask.size, value); + uint64_t offset = image->offset + image->cmask.offset; + uint64_t size; + + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + /* TODO: clear layers. */ + size = image->cmask.size; + } else { + offset += image->cmask.slice_size * range->baseArrayLayer; + size = image->cmask.slice_size * radv_get_layerCount(image, range); + } + + return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); } @@ -1578,6 +1588,13 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, VkClearColorValue clear_value = clear_att->clearValue.color; uint32_t clear_color[2], flush_bits = 0; uint32_t cmask_clear_value; + VkImageSubresourceRange range = { + .aspectMask = iview->aspect_mask, + .baseMipLevel = iview->base_mip, + .levelCount = iview->level_count, + .baseArrayLayer = iview->base_layer, + .layerCount = iview->layer_count, + }; if (pre_flush) { cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB | @@ -1595,13 +1612,6 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, uint32_t reset_value; bool can_avoid_fast_clear_elim; bool need_decompress_pass = false; - VkImageSubresourceRange range = { - .aspectMask = iview->aspect_mask, - .baseMipLevel = iview->base_mip, - .levelCount = iview->level_count, - .baseArrayLayer = iview->base_layer, - .layerCount = iview->layer_count, - }; vi_get_fast_clear_parameters(iview->vk_format, &clear_value, &reset_value, @@ -1609,7 +1619,7 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, if (radv_image_has_cmask(iview->image)) { flush_bits = radv_clear_cmask(cmd_buffer, iview->image, - cmask_clear_value); + &range, cmask_clear_value); need_decompress_pass = true; } @@ -1624,7 +1634,7 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, need_decompress_pass); } else { flush_bits = radv_clear_cmask(cmd_buffer, iview->image, - cmask_clear_value); + &range, cmask_clear_value); } if (post_flush) { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index fd7baa5f5b5..284d212d027 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1563,6 +1563,7 @@ struct radv_cmask_info { uint64_t size; unsigned alignment; unsigned slice_tile_max; + unsigned slice_size; }; |