summaryrefslogtreecommitdiffstats
path: root/src/amd/vulkan
diff options
context:
space:
mode:
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r--src/amd/vulkan/radv_descriptor_set.h2
-rw-r--r--src/amd/vulkan/radv_private.h6
-rw-r--r--src/amd/vulkan/radv_radeon_winsys.h2
3 files changed, 5 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_descriptor_set.h b/src/amd/vulkan/radv_descriptor_set.h
index 3aa07511d62..4b63992b2bb 100644
--- a/src/amd/vulkan/radv_descriptor_set.h
+++ b/src/amd/vulkan/radv_descriptor_set.h
@@ -38,9 +38,9 @@ struct radv_descriptor_set_binding_layout {
uint32_t buffer_offset;
uint16_t dynamic_offset_offset;
+ uint16_t dynamic_offset_count;
/* redundant with the type, each for a single array element */
uint32_t size;
- uint16_t dynamic_offset_count;
/* Offset in the radv_descriptor_set_layout of the immutable samplers, or 0
* if there are no immutable samplers. */
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 77592de3bdb..5028bf507b3 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -794,8 +794,6 @@ struct radv_cmd_buffer {
struct radv_cmd_buffer_upload upload;
- bool record_fail;
-
uint32_t scratch_size_needed;
uint32_t compute_scratch_size_needed;
uint32_t esgs_ring_size_needed;
@@ -803,6 +801,8 @@ struct radv_cmd_buffer {
bool tess_rings_needed;
bool sample_positions_needed;
+ bool record_fail;
+
int ring_offsets_idx; /* just used for verification */
};
@@ -1356,8 +1356,8 @@ struct radv_subpass_barrier {
struct radv_subpass {
uint32_t input_count;
- VkAttachmentReference * input_attachments;
uint32_t color_count;
+ VkAttachmentReference * input_attachments;
VkAttachmentReference * color_attachments;
VkAttachmentReference * resolve_attachments;
VkAttachmentReference depth_stencil_attachment;
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index 91c6bff72e2..84b1d73780b 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -172,9 +172,9 @@ struct radeon_surf_level {
uint32_t nblk_z;
uint32_t pitch_bytes;
uint32_t mode;
+ bool dcc_enabled;
uint64_t dcc_offset;
uint64_t dcc_fast_clear_size;
- bool dcc_enabled;
};