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-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c36
-rw-r--r--src/amd/vulkan/radv_cs.h22
-rw-r--r--src/amd/vulkan/radv_debug.c4
-rw-r--r--src/amd/vulkan/radv_debug.h2
-rw-r--r--src/amd/vulkan/radv_device.c26
-rw-r--r--src/amd/vulkan/radv_pipeline.c32
-rw-r--r--src/amd/vulkan/radv_private.h30
-rw-r--r--src/amd/vulkan/radv_query.c10
-rw-r--r--src/amd/vulkan/radv_radeon_winsys.h32
-rw-r--r--src/amd/vulkan/si_cmd_buffer.c26
-rw-r--r--src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c66
11 files changed, 143 insertions, 143 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ccaab63b84b..6134749d848 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -421,7 +421,7 @@ radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
}
static void
-radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
+radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
unsigned count, const uint32_t *data)
{
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
@@ -436,7 +436,7 @@ radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_device *device = cmd_buffer->device;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va;
va = radv_buffer_get_va(device->trace_bo);
@@ -486,7 +486,7 @@ radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline, enum ring_type ring)
{
struct radv_device *device = cmd_buffer->device;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t data[2];
uint64_t va;
@@ -536,7 +536,7 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
struct radv_descriptor_state *descriptors_state =
radv_get_descriptors_state(cmd_buffer, bind_point);
struct radv_device *device = cmd_buffer->device;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t data[MAX_SETS * 2] = {};
uint64_t va;
unsigned i;
@@ -589,7 +589,7 @@ radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
gl_shader_stage stage)
{
struct radv_device *device = cmd_buffer->device;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t sh_base = pipeline->user_data_0[stage];
struct radv_userdata_locations *locs =
&pipeline->shaders[stage]->info.user_sgprs_locs;
@@ -1183,7 +1183,7 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
{
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
struct radv_attachment_info *att;
uint32_t att_idx;
@@ -1223,7 +1223,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
VkClearDepthStencilValue ds_clear_value,
VkImageAspectFlags aspects)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(image->bo);
unsigned reg_offset = 0, reg_count = 0;
@@ -1262,7 +1262,7 @@ static void
radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
uint64_t va = radv_buffer_get_va(image->bo);
unsigned reg_offset = 0, reg_count = 0;
@@ -1331,7 +1331,7 @@ radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
{
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
struct radv_attachment_info *att;
uint32_t att_idx;
@@ -1360,7 +1360,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
int cb_idx,
uint32_t color_values[2])
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->clear_value_offset;
@@ -1388,7 +1388,7 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
int cb_idx)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->clear_value_offset;
@@ -1486,7 +1486,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
struct radv_cmd_state *state = &cmd_buffer->state;
if (state->index_type != state->last_index_type) {
@@ -1850,7 +1850,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
{
struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
struct radv_cmd_state *state = &cmd_buffer->state;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t ia_multi_vgt_param;
int32_t primitive_reset_en;
@@ -3087,7 +3087,7 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
uint64_t count_va,
uint32_t stride)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
: V_0287F0_DI_SRC_SEL_AUTO_INDEX;
bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
@@ -3175,7 +3175,7 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
{
struct radv_cmd_state *state = &cmd_buffer->state;
struct radeon_winsys *ws = cmd_buffer->device->ws;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
if (info->indirect) {
uint64_t va = radv_buffer_get_va(info->indirect->bo);
@@ -3643,7 +3643,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
struct radeon_winsys *ws = cmd_buffer->device->ws;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
struct radv_userdata_info *loc;
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
@@ -4202,7 +4202,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
VkPipelineStageFlags stageMask,
unsigned value)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(event->bo);
radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
@@ -4255,7 +4255,7 @@ void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
const VkImageMemoryBarrier* pImageMemoryBarriers)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
for (unsigned i = 0; i < eventCount; ++i) {
RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h
index 840597686a8..a5792fcc959 100644
--- a/src/amd/vulkan/radv_cs.h
+++ b/src/amd/vulkan/radv_cs.h
@@ -31,7 +31,7 @@
#include "sid.h"
static inline unsigned radeon_check_space(struct radeon_winsys *ws,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
unsigned needed)
{
if (cs->max_dw - cs->cdw < needed)
@@ -39,7 +39,7 @@ static inline unsigned radeon_check_space(struct radeon_winsys *ws,
return cs->cdw + needed;
}
-static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
{
assert(reg < SI_CONTEXT_REG_OFFSET);
assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -48,13 +48,13 @@ static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsign
radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
}
-static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
{
radeon_set_config_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
-static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
{
assert(reg >= SI_CONTEXT_REG_OFFSET);
assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -63,14 +63,14 @@ static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsig
radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
}
-static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
{
radeon_set_context_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
-static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
+static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
unsigned reg, unsigned idx,
unsigned value)
{
@@ -81,7 +81,7 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
radeon_emit(cs, value);
}
-static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
{
assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -90,13 +90,13 @@ static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned r
radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
}
-static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
{
radeon_set_sh_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
-static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
{
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -105,13 +105,13 @@ static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsig
radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
}
-static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
{
radeon_set_uconfig_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
-static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
+static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
unsigned reg, unsigned idx,
unsigned value)
{
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 5a9b43644ed..08fc80c12ab 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -80,7 +80,7 @@ radv_init_trace(struct radv_device *device)
}
static void
-radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
+radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs)
{
const char *filename = getenv("RADV_TRACE_FILE");
FILE *f = fopen(filename, "w");
@@ -660,7 +660,7 @@ radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
}
void
-radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
+radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
{
struct radv_pipeline *graphics_pipeline, *compute_pipeline;
struct radv_device *device = queue->device;
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 1e71349509e..f1b0dc26a63 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -64,7 +64,7 @@ bool
radv_init_trace(struct radv_device *device);
void
-radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs);
+radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs);
void
radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp);
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a537415812b..cf9cf437b3d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1892,7 +1892,7 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff
}
static void
-radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs,
+radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
struct radeon_winsys_bo *esgs_ring_bo,
uint32_t esgs_ring_size,
struct radeon_winsys_bo *gsvs_ring_bo,
@@ -1919,7 +1919,7 @@ radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs,
}
static void
-radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs *cs,
+radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
unsigned hs_offchip_param, unsigned tf_ring_size,
struct radeon_winsys_bo *tess_rings_bo)
{
@@ -1954,7 +1954,7 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs *cs
}
static void
-radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs *cs,
+radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
struct radeon_winsys_bo *compute_scratch_bo)
{
uint64_t scratch_va;
@@ -1974,7 +1974,7 @@ radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs *cs,
static void
radv_emit_global_shader_pointers(struct radv_queue *queue,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
struct radeon_winsys_bo *descriptor_bo)
{
uint64_t va;
@@ -2019,9 +2019,9 @@ radv_get_preamble_cs(struct radv_queue *queue,
uint32_t gsvs_ring_size,
bool needs_tess_rings,
bool needs_sample_positions,
- struct radeon_winsys_cs **initial_full_flush_preamble_cs,
- struct radeon_winsys_cs **initial_preamble_cs,
- struct radeon_winsys_cs **continue_preamble_cs)
+ struct radeon_cmdbuf **initial_full_flush_preamble_cs,
+ struct radeon_cmdbuf **initial_preamble_cs,
+ struct radeon_cmdbuf **continue_preamble_cs)
{
struct radeon_winsys_bo *scratch_bo = NULL;
struct radeon_winsys_bo *descriptor_bo = NULL;
@@ -2029,7 +2029,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
struct radeon_winsys_bo *esgs_ring_bo = NULL;
struct radeon_winsys_bo *gsvs_ring_bo = NULL;
struct radeon_winsys_bo *tess_rings_bo = NULL;
- struct radeon_winsys_cs *dest_cs[3] = {0};
+ struct radeon_cmdbuf *dest_cs[3] = {0};
bool add_tess_rings = false, add_sample_positions = false;
unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
unsigned max_offchip_buffers;
@@ -2154,7 +2154,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
descriptor_bo = queue->descriptor_bo;
for(int i = 0; i < 3; ++i) {
- struct radeon_winsys_cs *cs = NULL;
+ struct radeon_cmdbuf *cs = NULL;
cs = queue->device->ws->cs_create(queue->device->ws,
queue->queue_family_index ? RING_COMPUTE : RING_GFX);
if (!cs)
@@ -2467,7 +2467,7 @@ VkResult radv_QueueSubmit(
uint32_t scratch_size = 0;
uint32_t compute_scratch_size = 0;
uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
- struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
+ struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
VkResult result;
bool fence_emitted = false;
bool tess_rings_needed = false;
@@ -2498,7 +2498,7 @@ VkResult radv_QueueSubmit(
return result;
for (uint32_t i = 0; i < submitCount; i++) {
- struct radeon_winsys_cs **cs_array;
+ struct radeon_cmdbuf **cs_array;
bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
bool can_patch = true;
uint32_t advance;
@@ -2531,7 +2531,7 @@ VkResult radv_QueueSubmit(
continue;
}
- cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
+ cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
(pSubmits[i].commandBufferCount));
for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
@@ -2547,7 +2547,7 @@ VkResult radv_QueueSubmit(
}
for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
- struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
+ struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
const struct radv_winsys_bo_list *bo_list = NULL;
advance = MIN2(max_cs_submission,
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 113622bb0ce..70a8c63c926 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2493,7 +2493,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
}
static void
-radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_binning_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
@@ -2549,7 +2549,7 @@ radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
static void
-radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_create_info *extra)
@@ -2631,7 +2631,7 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_blend_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_blend_state *blend)
{
@@ -2658,7 +2658,7 @@ radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
static void
-radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
@@ -2699,7 +2699,7 @@ radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
static void
-radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_multisample_state *ms = &pipeline->graphics.ms;
@@ -2742,7 +2742,7 @@ radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline)
{
const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
@@ -2766,7 +2766,7 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader)
{
@@ -2825,7 +2825,7 @@ radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader)
{
@@ -2839,7 +2839,7 @@ radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader,
const struct radv_tessellation_state *tess)
@@ -2862,7 +2862,7 @@ radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader,
const struct radv_tessellation_state *tess)
@@ -2888,7 +2888,7 @@ radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_tessellation_state *tess)
{
@@ -2908,7 +2908,7 @@ radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_tessellation_state *tess)
{
@@ -2941,7 +2941,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_gs_state *gs_state)
{
@@ -3021,7 +3021,7 @@ static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
}
static void
-radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
@@ -3108,7 +3108,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
}
static void
-radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps;
@@ -3151,7 +3151,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
}
static void
-radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index cc839cf6222..cc336499c73 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -598,9 +598,9 @@ struct radv_queue {
struct radeon_winsys_bo *esgs_ring_bo;
struct radeon_winsys_bo *gsvs_ring_bo;
struct radeon_winsys_bo *tess_rings_bo;
- struct radeon_winsys_cs *initial_preamble_cs;
- struct radeon_winsys_cs *initial_full_flush_preamble_cs;
- struct radeon_winsys_cs *continue_preamble_cs;
+ struct radeon_cmdbuf *initial_preamble_cs;
+ struct radeon_cmdbuf *initial_full_flush_preamble_cs;
+ struct radeon_cmdbuf *continue_preamble_cs;
};
struct radv_bo_list {
@@ -621,7 +621,7 @@ struct radv_device {
struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
int queue_count[RADV_MAX_QUEUE_FAMILIES];
- struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
+ struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
bool always_use_syncobj;
bool has_distributed_tess;
@@ -1007,7 +1007,7 @@ struct radv_cmd_buffer {
VkCommandBufferUsageFlags usage_flags;
VkCommandBufferLevel level;
enum radv_cmd_buffer_status status;
- struct radeon_winsys_cs *cs;
+ struct radeon_cmdbuf *cs;
struct radv_cmd_state state;
struct radv_vertex_binding vertex_bindings[MAX_VBS];
uint32_t queue_family_index;
@@ -1050,15 +1050,15 @@ void si_init_config(struct radv_cmd_buffer *cmd_buffer);
void cik_create_gfx_config(struct radv_device *device);
-void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
+void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
int count, const VkViewport *viewports);
-void si_write_scissors(struct radeon_winsys_cs *cs, int first,
+void si_write_scissors(struct radeon_cmdbuf *cs, int first,
int count, const VkRect2D *scissors,
const VkViewport *viewports, bool can_use_guardband);
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool instanced_draw, bool indirect_draw,
uint32_t draw_vertex_count);
-void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
+void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
bool predicated,
enum chip_class chip_class,
bool is_mec,
@@ -1068,11 +1068,11 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
uint32_t old_fence,
uint32_t new_fence);
-void si_emit_wait_fence(struct radeon_winsys_cs *cs,
+void si_emit_wait_fence(struct radeon_cmdbuf *cs,
bool predicated,
uint64_t va, uint32_t ref,
uint32_t mask);
-void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
+void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
uint32_t *fence_ptr, uint64_t va,
bool is_mec,
@@ -1106,7 +1106,7 @@ void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
-void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
+void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
unsigned radv_cayman_get_maxdist(int log_samples);
void radv_device_init_msaa(struct radv_device *device);
@@ -1132,7 +1132,7 @@ bool radv_get_memory_fd(struct radv_device *device,
int *pFD);
static inline void
-radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
+radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
unsigned sh_offset, unsigned pointer_count,
bool use_32bit_pointers)
{
@@ -1142,7 +1142,7 @@ radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
static inline void
radv_emit_shader_pointer_body(struct radv_device *device,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
uint64_t va, bool use_32bit_pointers)
{
radeon_emit(cs, va);
@@ -1157,7 +1157,7 @@ radv_emit_shader_pointer_body(struct radv_device *device,
static inline void
radv_emit_shader_pointer(struct radv_device *device,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
uint32_t sh_offset, uint64_t va, bool global)
{
bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
@@ -1272,7 +1272,7 @@ struct radv_pipeline {
struct radv_shader_variant *gs_copy_shader;
VkShaderStageFlags active_stages;
- struct radeon_winsys_cs cs;
+ struct radeon_cmdbuf cs;
struct radv_vertex_elements_info vertex_elements;
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index f30796446d9..559b7cd49dc 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -950,7 +950,7 @@ void radv_CmdCopyQueryPoolResults(
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
unsigned elem_size = (flags & VK_QUERY_RESULT_64_BIT) ? 8 : 4;
uint64_t va = radv_buffer_get_va(pool->bo);
uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo);
@@ -1082,7 +1082,7 @@ static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
VkQueryType query_type,
VkQueryControlFlags flags)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
switch (query_type) {
case VK_QUERY_TYPE_OCCLUSION:
radeon_check_space(cmd_buffer->device->ws, cs, 7);
@@ -1133,7 +1133,7 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
uint64_t va, uint64_t avail_va,
VkQueryType query_type)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
switch (query_type) {
case VK_QUERY_TYPE_OCCLUSION:
radeon_check_space(cmd_buffer->device->ws, cs, 14);
@@ -1184,7 +1184,7 @@ void radv_CmdBeginQuery(
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(pool->bo);
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
@@ -1253,7 +1253,7 @@ void radv_CmdWriteTimestamp(
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(pool->bo);
uint64_t avail_va = va + pool->availability_offset + 4 * query;
uint64_t query_va = va + pool->stride * query;
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index 2ebd18cf905..8b723e9fb88 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -96,7 +96,7 @@ enum radeon_value_id {
RADEON_CURRENT_MCLK,
};
-struct radeon_winsys_cs {
+struct radeon_cmdbuf {
unsigned cdw; /* Number of used dwords. */
unsigned max_dw; /* Maximum number of dwords. */
uint32_t *buf; /* The base pointer of the chunk. */
@@ -234,36 +234,36 @@ struct radeon_winsys {
bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
enum ring_type ring_type, int ring_index);
- struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
+ struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
enum ring_type ring_type);
- void (*cs_destroy)(struct radeon_winsys_cs *cs);
+ void (*cs_destroy)(struct radeon_cmdbuf *cs);
- void (*cs_reset)(struct radeon_winsys_cs *cs);
+ void (*cs_reset)(struct radeon_cmdbuf *cs);
- bool (*cs_finalize)(struct radeon_winsys_cs *cs);
+ bool (*cs_finalize)(struct radeon_cmdbuf *cs);
- void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
+ void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
int (*cs_submit)(struct radeon_winsys_ctx *ctx,
int queue_index,
- struct radeon_winsys_cs **cs_array,
+ struct radeon_cmdbuf **cs_array,
unsigned cs_count,
- struct radeon_winsys_cs *initial_preamble_cs,
- struct radeon_winsys_cs *continue_preamble_cs,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
struct radv_winsys_sem_info *sem_info,
const struct radv_winsys_bo_list *bo_list, /* optional */
bool can_patch,
struct radeon_winsys_fence *fence);
- void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
+ void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
struct radeon_winsys_bo *bo,
uint8_t priority);
- void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
- struct radeon_winsys_cs *child);
+ void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
+ struct radeon_cmdbuf *child);
- void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count);
+ void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
int (*surface_init)(struct radeon_winsys *ws,
const struct ac_surf_info *surf_info,
@@ -307,12 +307,12 @@ struct radeon_winsys {
};
-static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
+static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
{
cs->buf[cs->cdw++] = value;
}
-static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
+static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
const uint32_t *values, unsigned count)
{
memcpy(cs->buf + cs->cdw, values, count * 4);
@@ -325,7 +325,7 @@ static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
}
static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
struct radeon_winsys_bo *bo,
uint8_t priority)
{
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 4c3a888f3cf..0692124bf51 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -37,7 +37,7 @@
static void
si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
unsigned raster_config,
unsigned raster_config_1)
{
@@ -81,7 +81,7 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
static void
si_emit_compute(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs)
+ struct radeon_cmdbuf *cs)
{
radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
radeon_emit(cs, 0);
@@ -135,7 +135,7 @@ static unsigned radv_pack_float_12p4(float x)
static void
si_set_raster_config(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs)
+ struct radeon_cmdbuf *cs)
{
unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
@@ -163,7 +163,7 @@ si_set_raster_config(struct radv_physical_device *physical_device,
static void
si_emit_config(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs)
+ struct radeon_cmdbuf *cs)
{
int i;
@@ -399,7 +399,7 @@ void si_init_config(struct radv_cmd_buffer *cmd_buffer)
void
cik_create_gfx_config(struct radv_device *device)
{
- struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
+ struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
if (!cs)
return;
@@ -456,7 +456,7 @@ get_viewport_xform(const VkViewport *viewport,
}
void
-si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
+si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
int count, const VkViewport *viewports)
{
int i;
@@ -515,7 +515,7 @@ static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
}
void
-si_write_scissors(struct radeon_winsys_cs *cs, int first,
+si_write_scissors(struct radeon_cmdbuf *cs, int first,
int count, const VkRect2D *scissors,
const VkViewport *viewports, bool can_use_guardband)
{
@@ -672,7 +672,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
}
-void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
+void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
bool predicated,
enum chip_class chip_class,
bool is_mec,
@@ -722,7 +722,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
}
void
-si_emit_wait_fence(struct radeon_winsys_cs *cs,
+si_emit_wait_fence(struct radeon_cmdbuf *cs,
bool predicated,
uint64_t va, uint32_t ref,
uint32_t mask)
@@ -737,7 +737,7 @@ si_emit_wait_fence(struct radeon_winsys_cs *cs,
}
static void
-si_emit_acquire_mem(struct radeon_winsys_cs *cs,
+si_emit_acquire_mem(struct radeon_cmdbuf *cs,
bool is_mec,
bool predicated,
bool is_gfx9,
@@ -764,7 +764,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs,
}
void
-si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
+si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
uint32_t *flush_cnt,
uint64_t flush_va,
@@ -1039,7 +1039,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
uint64_t dst_va, uint64_t src_va,
unsigned size, unsigned flags)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t header = 0, command = 0;
assert(size);
@@ -1317,7 +1317,7 @@ unsigned radv_cayman_get_maxdist(int log_samples)
return max_dist[log_samples];
}
-void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
+void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
{
switch (nr_samples) {
default:
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 0cd870b7c89..848e81924ff 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -41,7 +41,7 @@ enum {
};
struct radv_amdgpu_cs {
- struct radeon_winsys_cs base;
+ struct radeon_cmdbuf base;
struct radv_amdgpu_winsys *ws;
struct amdgpu_cs_ib_info ib;
@@ -70,12 +70,12 @@ struct radv_amdgpu_cs {
int *virtual_buffer_hash_table;
/* For chips that don't support chaining. */
- struct radeon_winsys_cs *old_cs_buffers;
+ struct radeon_cmdbuf *old_cs_buffers;
unsigned num_old_cs_buffers;
};
static inline struct radv_amdgpu_cs *
-radv_amdgpu_cs(struct radeon_winsys_cs *base)
+radv_amdgpu_cs(struct radeon_cmdbuf *base)
{
return (struct radv_amdgpu_cs*)base;
}
@@ -193,7 +193,7 @@ static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws,
return false;
}
-static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
+static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
@@ -206,7 +206,7 @@ static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
- struct radeon_winsys_cs *rcs = &cs->old_cs_buffers[i];
+ struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
free(rcs->buf);
}
@@ -229,7 +229,7 @@ static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
cs->hw_ip = ring_to_hw_ip(ring_type);
}
-static struct radeon_winsys_cs *
+static struct radeon_cmdbuf *
radv_amdgpu_cs_create(struct radeon_winsys *ws,
enum ring_type ring_type)
{
@@ -279,7 +279,7 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws,
return &cs->base;
}
-static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size)
+static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
@@ -401,7 +401,7 @@ static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size)
}
-static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs *_cs)
+static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
@@ -417,7 +417,7 @@ static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs *_cs)
return !cs->failed;
}
-static void radv_amdgpu_cs_reset(struct radeon_winsys_cs *_cs)
+static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
cs->base.cdw = 0;
@@ -449,7 +449,7 @@ static void radv_amdgpu_cs_reset(struct radeon_winsys_cs *_cs)
cs->ib.size = 0;
} else {
for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
- struct radeon_winsys_cs *rcs = &cs->old_cs_buffers[i];
+ struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
free(rcs->buf);
}
@@ -509,7 +509,7 @@ static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
++cs->num_buffers;
}
-static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs *_cs,
+static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
struct radeon_winsys_bo *bo,
uint8_t priority)
{
@@ -552,7 +552,7 @@ static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs *_cs,
}
-static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs,
+static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
struct radeon_winsys_bo *_bo,
uint8_t priority)
{
@@ -570,8 +570,8 @@ static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs,
radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority);
}
-static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs *_parent,
- struct radeon_winsys_cs *_child)
+static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
+ struct radeon_cmdbuf *_child)
{
struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
@@ -604,11 +604,11 @@ static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs *_parent,
}
static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
- struct radeon_winsys_cs **cs_array,
+ struct radeon_cmdbuf **cs_array,
unsigned count,
struct radv_amdgpu_winsys_bo **extra_bo_array,
unsigned num_extra_bo,
- struct radeon_winsys_cs *extra_cs,
+ struct radeon_cmdbuf *extra_cs,
const struct radv_winsys_bo_list *radv_bo_list,
amdgpu_bo_list_handle *bo_list)
{
@@ -794,10 +794,10 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
int queue_idx,
struct radv_winsys_sem_info *sem_info,
const struct radv_winsys_bo_list *radv_bo_list,
- struct radeon_winsys_cs **cs_array,
+ struct radeon_cmdbuf **cs_array,
unsigned cs_count,
- struct radeon_winsys_cs *initial_preamble_cs,
- struct radeon_winsys_cs *continue_preamble_cs,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
struct radeon_winsys_fence *_fence)
{
int r;
@@ -876,10 +876,10 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
int queue_idx,
struct radv_winsys_sem_info *sem_info,
const struct radv_winsys_bo_list *radv_bo_list,
- struct radeon_winsys_cs **cs_array,
+ struct radeon_cmdbuf **cs_array,
unsigned cs_count,
- struct radeon_winsys_cs *initial_preamble_cs,
- struct radeon_winsys_cs *continue_preamble_cs,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
struct radeon_winsys_fence *_fence)
{
int r;
@@ -893,7 +893,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
for (unsigned i = 0; i < cs_count;) {
struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[i]);
struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
- struct radeon_winsys_cs *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
+ struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
unsigned cnt = MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT - !!preamble_cs,
cs_count - i);
@@ -958,10 +958,10 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
int queue_idx,
struct radv_winsys_sem_info *sem_info,
const struct radv_winsys_bo_list *radv_bo_list,
- struct radeon_winsys_cs **cs_array,
+ struct radeon_cmdbuf **cs_array,
unsigned cs_count,
- struct radeon_winsys_cs *initial_preamble_cs,
- struct radeon_winsys_cs *continue_preamble_cs,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
struct radeon_winsys_fence *_fence)
{
int r;
@@ -983,7 +983,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = {0};
unsigned number_of_ibs = 1;
struct radeon_winsys_bo *bos[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = {0};
- struct radeon_winsys_cs *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
+ struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
uint32_t *ptr;
unsigned cnt = 0;
@@ -996,7 +996,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
* IB per submit.
*/
unsigned new_cs_count = cs->num_old_cs_buffers + 1;
- struct radeon_winsys_cs *new_cs_array[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
+ struct radeon_cmdbuf *new_cs_array[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
unsigned idx = 0;
for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
@@ -1004,7 +1004,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
new_cs_array[idx++] = cs_array[i];
for (unsigned j = 0; j < new_cs_count; j++) {
- struct radeon_winsys_cs *rcs = new_cs_array[j];
+ struct radeon_cmdbuf *rcs = new_cs_array[j];
bool needs_preamble = preamble_cs && j == 0;
unsigned size = 0;
@@ -1134,10 +1134,10 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
int queue_idx,
- struct radeon_winsys_cs **cs_array,
+ struct radeon_cmdbuf **cs_array,
unsigned cs_count,
- struct radeon_winsys_cs *initial_preamble_cs,
- struct radeon_winsys_cs *continue_preamble_cs,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
struct radv_winsys_sem_info *sem_info,
const struct radv_winsys_bo_list *bo_list,
bool can_patch,
@@ -1196,7 +1196,7 @@ static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
return ret;
}
-static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs,
+static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs,
FILE* file,
const int *trace_ids, int trace_id_count)
{
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 10:18:26 +0000