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Diffstat (limited to 'src/amd/vulkan/radv_radeon_winsys.h')
-rw-r--r--src/amd/vulkan/radv_radeon_winsys.h55
1 files changed, 1 insertions, 54 deletions
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index 855a2d712af..397f28e3c46 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -35,6 +35,7 @@
#include "main/macros.h"
#include "amd_family.h"
+struct radeon_info;
struct ac_surf_info;
struct radeon_surf;
@@ -74,60 +75,6 @@ struct radeon_winsys_cs {
uint32_t *buf; /* The base pointer of the chunk. */
};
-struct radeon_info {
- /* PCI info: domain:bus:dev:func */
- uint32_t pci_domain;
- uint32_t pci_bus;
- uint32_t pci_dev;
- uint32_t pci_func;
-
- /* Device info. */
- uint32_t pci_id;
- enum radeon_family family;
- enum chip_class chip_class;
- uint32_t gart_page_size;
- uint64_t gart_size;
- uint64_t vram_size;
- uint64_t visible_vram_size;
- bool has_dedicated_vram;
- bool has_virtual_memory;
- bool gfx_ib_pad_with_type2;
- bool has_uvd;
- uint32_t sdma_rings;
- uint32_t compute_rings;
- uint32_t vce_fw_version;
- uint32_t vce_harvest_config;
- uint32_t clock_crystal_freq; /* in kHz */
-
- /* Kernel info. */
- uint32_t drm_major; /* version */
- uint32_t drm_minor;
- uint32_t drm_patchlevel;
- bool has_userptr;
-
- /* Shader cores. */
- uint32_t r600_max_quad_pipes; /* wave size / 16 */
- uint32_t max_shader_clock;
- uint32_t num_good_compute_units;
- uint32_t max_se; /* shader engines */
- uint32_t max_sh_per_se; /* shader arrays per shader engine */
-
- /* Render backends (color + depth blocks). */
- uint32_t r300_num_gb_pipes;
- uint32_t r300_num_z_pipes;
- uint32_t r600_gb_backend_map; /* R600 harvest config */
- bool r600_gb_backend_map_valid;
- uint32_t r600_num_banks;
- uint32_t num_render_backends;
- uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
- uint32_t pipe_interleave_bytes;
- uint32_t enabled_rb_mask; /* GCN harvest config */
-
- /* Tile modes. */
- uint32_t si_tile_mode_array[32];
- uint32_t cik_macrotile_mode_array[16];
-};
-
#define RADEON_SURF_TYPE_MASK 0xFF
#define RADEON_SURF_TYPE_SHIFT 0
#define RADEON_SURF_TYPE_1D 0