diff options
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 49 |
1 files changed, 48 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index ae269c32c49..b49e6d2b2e4 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2686,12 +2686,26 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *cs, pipeline->graphics.cb_target_mask = blend->cb_target_mask; } +static const VkConservativeRasterizationModeEXT +radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo) +{ + const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster = + vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT); + + if (!conservative_raster) + return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT; + return conservative_raster->conservativeRasterizationMode; +} static void radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs, + struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState; + const VkConservativeRasterizationModeEXT mode = + radv_get_conservative_raster_mode(vkraster); + uint32_t pa_sc_conservative_rast = 0; radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, S_028810_PS_UCP_MODE(3) | @@ -2725,6 +2739,39 @@ radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs, S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0)); + + /* Conservative rasterization. */ + if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) { + struct radv_multisample_state *ms = &pipeline->graphics.ms; + + ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1); + ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) | + S_028804_OVERRASTERIZATION_AMOUNT(4); + + pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | + S_028C4C_POSTZ_AA_MASK_ENABLE(1) | + S_028C4C_CENTROID_SAMPLE_OVERRIDE(1); + + if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) { + pa_sc_conservative_rast |= + S_028C4C_OVER_RAST_ENABLE(1) | + S_028C4C_OVER_RAST_SAMPLE_SELECT(0) | + S_028C4C_UNDER_RAST_ENABLE(0) | + S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) | + S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1); + } else { + assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT); + pa_sc_conservative_rast |= + S_028C4C_OVER_RAST_ENABLE(0) | + S_028C4C_OVER_RAST_SAMPLE_SELECT(1) | + S_028C4C_UNDER_RAST_ENABLE(1) | + S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) | + S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0); + } + } + + radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, + pa_sc_conservative_rast); } @@ -3255,7 +3302,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra); radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend); - radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo); + radv_pipeline_generate_raster_state(&pipeline->cs, pipeline, pCreateInfo); radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline); radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline); radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess); |