diff options
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 557d5ec58b3..01808cc3f55 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -62,7 +62,6 @@ struct radv_blend_state { struct radv_tessellation_state { uint32_t ls_hs_config; - uint32_t tcs_out_layout; uint32_t tcs_out_offsets; uint32_t offchip_layout; unsigned num_patches; @@ -1382,8 +1381,6 @@ calculate_tess_state(struct radv_pipeline *pipeline, tess.lds_size = lds_size; - tess.tcs_out_layout = (output_patch_size / 4) | - ((output_vertex_size / 4) << 13); tess.tcs_out_offsets = (output_patch0_offset / 16) | ((perpatch_output_offset / 16) << 16); tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) | @@ -2615,12 +2612,11 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs, loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT); if (loc->sgpr_idx != -1) { uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL]; - assert(loc->num_sgprs == 3); + assert(loc->num_sgprs == 2); assert(!loc->indirect); - radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 3); + radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 2); radeon_emit(cs, tess->offchip_layout); radeon_emit(cs, tess->tcs_out_offsets); - radeon_emit(cs, tess->tcs_out_layout); } loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT); |