diff options
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 3 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index ec7b74aaaf4..6c91a5bd848 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -457,6 +457,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9; + info->has_out_of_order_rast = info->chip_class >= GFX8 && + info->max_se >= 2; + /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */ info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 || (info->chip_class >= GFX8 && diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 10a3205f44d..ea6b9111108 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -63,6 +63,7 @@ struct radeon_info { bool has_dcc_constant_encode; bool has_rbplus; /* if RB+ registers exist */ bool has_load_ctx_reg_pkt; + bool has_out_of_order_rast; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ |