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-rw-r--r--src/amd/common/ac_gpu_info.c3
-rw-r--r--src/amd/common/ac_gpu_info.h1
2 files changed, 4 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index b6b37564c9f..50e92a405e3 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -454,6 +454,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->family == CHIP_RENOIR ||
info->chip_class >= GFX10;
+ info->has_rbplus = info->family == CHIP_STONEY ||
+ info->chip_class >= GFX9;
+
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 10b578a1ef9..173cc82084a 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -61,6 +61,7 @@ struct radeon_info {
bool has_clear_state;
bool has_distributed_tess;
bool has_dcc_constant_encode;
+ bool has_rbplus; /* if RB+ registers exist */
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */