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-rw-r--r--src/amd/common/ac_surface.c6
-rw-r--r--src/amd/common/ac_surface.h2
2 files changed, 5 insertions, 3 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 61b4e41a3ba..68700f41024 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -30,6 +30,7 @@
#include "amdgpu_id.h"
#include "ac_gpu_info.h"
#include "util/macros.h"
+#include "util/u_atomic.h"
#include "util/u_math.h"
#include <errno.h>
@@ -706,13 +707,14 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
/* Work out tile swizzle. */
- if (surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
+ if (config->info.surf_index &&
+ surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
!(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
(config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
- AddrBaseSwizzleIn.surfIndex = config->info.surf_index;
+ AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex;
AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 01a71f32b2f..b2620f95055 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -209,10 +209,10 @@ struct ac_surf_info {
uint32_t width;
uint32_t height;
uint32_t depth;
- uint32_t surf_index;
uint8_t samples;
uint8_t levels;
uint16_t array_size;
+ uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
};
struct ac_surf_config {