diff options
Diffstat (limited to 'src/amd/common/ac_surface.c')
-rw-r--r-- | src/amd/common/ac_surface.c | 86 |
1 files changed, 74 insertions, 12 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index b2af1f70b69..b7423e5b520 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -227,8 +227,16 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, return addrCreateOutput.hLib; } -static int surf_config_sanity(const struct ac_surf_config *config) +static int surf_config_sanity(const struct ac_surf_config *config, + unsigned flags) { + /* FMASK is allocated together with the color surface and can't be + * allocated separately. + */ + assert(!(flags & RADEON_SURF_FMASK)); + if (flags & RADEON_SURF_FMASK) + return -EINVAL; + /* all dimension must be at least 1 ! */ if (!config->info.width || !config->info.height || !config->info.depth || !config->info.array_size || !config->info.levels) @@ -445,7 +453,6 @@ static bool get_display_flag(const struct ac_surf_config *config, unsigned bpe = surf->bpe; if (surf->flags & RADEON_SURF_SCANOUT && - !(surf->flags & RADEON_SURF_FMASK) && config->info.samples <= 1 && surf->blk_w <= 2 && surf->blk_h == 1) { /* subsampled */ @@ -556,9 +563,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, compressed = surf->blk_w == 4 && surf->blk_h == 4; - /* MSAA and FMASK require 2D tiling. */ - if (config->info.samples > 1 || - (surf->flags & RADEON_SURF_FMASK)) + /* MSAA requires 2D tiling. */ + if (config->info.samples > 1) mode = RADEON_SURF_MODE_2D; /* DB doesn't support linear layouts. */ @@ -607,7 +613,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, /* Set the micro tile type. */ if (surf->flags & RADEON_SURF_SCANOUT) AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE; - else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK)) + else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER; else AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE; @@ -615,7 +621,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER); AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0; AddrSurfInfoIn.flags.cube = config->is_cube; - AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0; AddrSurfInfoIn.flags.display = get_display_flag(config, surf); AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1; AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0; @@ -680,8 +685,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw && surf->u.legacy.bankh && surf->u.legacy.mtilea && surf->u.legacy.tile_split) { - assert(!(surf->flags & RADEON_SURF_FMASK)); - /* If any of these parameters are incorrect, the calculation * will fail. */ AddrTileInfoIn.banks = surf->u.legacy.num_banks; @@ -828,6 +831,67 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, } } + /* Compute FMASK. */ + if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) { + ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0}; + ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0}; + ADDR_TILEINFO fmask_tile_info = {}; + + fin.size = sizeof(fin); + fout.size = sizeof(fout); + + fin.tileMode = AddrSurfInfoOut.tileMode; + fin.pitch = AddrSurfInfoOut.pitch; + fin.height = config->info.height; + fin.numSlices = AddrSurfInfoIn.numSlices; + fin.numSamples = AddrSurfInfoIn.numSamples; + fin.numFrags = AddrSurfInfoIn.numFrags; + fin.tileIndex = AddrSurfInfoOut.tileIndex; + fout.pTileInfo = &fmask_tile_info; + + r = AddrComputeFmaskInfo(addrlib, &fin, &fout); + if (r) + return r; + + surf->u.legacy.fmask.size = fout.fmaskBytes; + surf->u.legacy.fmask.alignment = fout.baseAlign; + surf->u.legacy.fmask.tile_swizzle = 0; + + surf->u.legacy.fmask.slice_tile_max = + (fout.pitch * fout.height) / 64; + if (surf->u.legacy.fmask.slice_tile_max) + surf->u.legacy.fmask.slice_tile_max -= 1; + + surf->u.legacy.fmask.tiling_index = fout.tileIndex; + surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight; + surf->u.legacy.fmask.pitch_in_pixels = fout.pitch; + + /* Compute tile swizzle for FMASK. */ + if (config->info.fmask_surf_index && + !(surf->flags & RADEON_SURF_SHAREABLE)) { + ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0}; + ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0}; + + xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT); + xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT); + + /* This counter starts from 1 instead of 0. */ + xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index); + xin.tileIndex = fout.tileIndex; + xin.macroModeIndex = fout.macroModeIndex; + xin.pTileInfo = fout.pTileInfo; + xin.tileMode = fin.tileMode; + + int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout); + if (r != ADDR_OK) + return r; + + assert(xout.tileSwizzle <= + u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); + surf->u.legacy.fmask.tile_swizzle = xout.tileSwizzle; + } + } + /* Recalculate the whole DCC miptree size including disabled levels. * This is what addrlib does, but calling addrlib would be a lot more * complicated. @@ -1197,8 +1261,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0}; int r; - assert(!(surf->flags & RADEON_SURF_FMASK)); - AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT); compressed = surf->blk_w == 4 && surf->blk_h == 4; @@ -1422,7 +1484,7 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, { int r; - r = surf_config_sanity(config); + r = surf_config_sanity(config, surf->flags); if (r) return r; |