1 files changed, 30 insertions, 4 deletions

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index b294cd85259..1b4d72e31bd 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -415,6 +415,31 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 	return index;
 }
 
+static bool get_display_flag(const struct ac_surf_config *config,
+			     const struct radeon_surf *surf)
+{
+	unsigned num_channels = config->info.num_channels;
+	unsigned bpe = surf->bpe;
+
+	if (surf->flags & RADEON_SURF_SCANOUT &&
+	    !(surf->flags & RADEON_SURF_FMASK) &&
+	    config->info.samples <= 1 &&
+	    surf->blk_w <= 2 && surf->blk_h == 1) {
+		/* subsampled */
+		if (surf->blk_w == 2 && surf->blk_h == 1)
+			return true;
+
+		if  (/* RGBA8 or RGBA16F */
+		     (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
+		     /* R5G6B5 or R5G5B5A1 */
+		     (bpe == 2 && num_channels >= 3) ||
+		     /* C8 palette */
+		     (bpe == 1 && num_channels == 1))
+			return true;
+	}
+	return false;
+}
+
 /**
  * This must be called after the first level is computed.
  *
@@ -449,7 +474,7 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib,
 	    config->info.surf_index &&
 	    surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
 	    !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
-	    (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
+	    !get_display_flag(config, surf)) {
 		ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
 		ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
 
@@ -568,7 +593,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 	AddrSurfInfoIn.flags.cube = config->is_cube;
 	AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
-	AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
+	AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
 	AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
 	AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 
@@ -848,6 +873,7 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 		sin.preferredSwSet.sw_S = 1;
 
 	if (is_fmask) {
+		sin.flags.display = 0;
 		sin.flags.color = 0;
 		sin.flags.fmask = 1;
 	}
@@ -943,7 +969,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 		    in->swizzleMode >= ADDR_SW_64KB_Z_T &&
 		    !out.mipChainInTail &&
 		    !(surf->flags & RADEON_SURF_SHAREABLE) &&
-		    (in->numSamples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
+		    !in->flags.display) {
 			ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
 			ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
 
@@ -1196,7 +1222,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
 	AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 	AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
-	AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
+	AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
 	/* flags.texture currently refers to TC-compatible HTILE */
 	AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
 				       surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;