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-rw-r--r--src/amd/common/ac_gpu_info.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 9986d58202a..555f7175e87 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -66,6 +66,7 @@ struct radeon_info {
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
bool cpdma_prefetch_writes_memory;
+ uint32_t pbb_max_alloc_count;
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */