diff options
Diffstat (limited to 'src/amd/addrlib')
| -rw-r--r-- | src/amd/addrlib/addrinterface.h | 3 | ||||
| -rw-r--r-- | src/amd/addrlib/core/addrcommon.h | 3 | ||||
| -rw-r--r-- | src/amd/addrlib/core/addrlib.cpp | 5 |
3 files changed, 8 insertions, 3 deletions
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h index 764377a4b47..c6c46845fd5 100644 --- a/src/amd/addrlib/addrinterface.h +++ b/src/amd/addrlib/addrinterface.h @@ -446,7 +446,8 @@ typedef union _ADDR_SURFACE_FLAGS /// This flag indicates we need to follow the alignment with /// CZ families or other ASICs under PX configuration + CZ. UINT_32 nonSplit : 1; ///< CI: depth texture should not be split - UINT_32 reserved : 10; ///< Reserved bits + UINT_32 disableLinearOpt: 1; ///< Disable tile mode optimization to linear + UINT_32 reserved : 9; ///< Reserved bits }; UINT_32 value; diff --git a/src/amd/addrlib/core/addrcommon.h b/src/amd/addrlib/core/addrcommon.h index 88cbad0b3ba..60b3d818f72 100644 --- a/src/amd/addrlib/core/addrcommon.h +++ b/src/amd/addrlib/core/addrcommon.h @@ -133,7 +133,8 @@ union ADDR_CONFIG_FLAGS UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize - UINT_32 reserved : 23; ///< Reserved bits for future use + UINT_32 disableLinearOpt : 1; ///< Disallow tile modes to be optimized to linear + UINT_32 reserved : 22; ///< Reserved bits for future use }; UINT_32 value; diff --git a/src/amd/addrlib/core/addrlib.cpp b/src/amd/addrlib/core/addrlib.cpp index 4804b0d79d9..f1a9fcbe30a 100644 --- a/src/amd/addrlib/core/addrlib.cpp +++ b/src/amd/addrlib/core/addrlib.cpp @@ -265,6 +265,7 @@ ADDR_E_RETURNCODE AddrLib::Create( pLib->m_configFlags.checkLast2DLevel = pCreateIn->createFlags.checkLast2DLevel; pLib->m_configFlags.useHtileSliceAlign = pCreateIn->createFlags.useHtileSliceAlign; pLib->m_configFlags.allowLargeThickTile = pCreateIn->createFlags.allowLargeThickTile; + pLib->m_configFlags.disableLinearOpt = FALSE; pLib->SetAddrChipFamily(pCreateIn->chipFamily, pCreateIn->chipRevision); @@ -3554,7 +3555,9 @@ BOOL_32 AddrLib::OptimizeTileMode( (IsLinear(tileMode) == FALSE) && (AddrElemLib::IsBlockCompressed(pIn->format) == FALSE) && (pIn->flags.depth == FALSE) && - (pIn->flags.stencil == FALSE)) + (pIn->flags.stencil == FALSE) && + (m_configFlags.disableLinearOpt == FALSE) && + (pIn->flags.disableLinearOpt == FALSE)) { tileMode = ADDR_TM_LINEAR_ALIGNED; } |